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PM5342-BGI PDF预览

PM5342-BGI

更新时间: 2024-11-06 13:12:27
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PMC ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
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2页 49K
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PM5342-BGI 数据手册

 浏览型号PM5342-BGI的Datasheet PDF文件第2页 
PM5342  
PMC-Sierra,Inc.  
SPECTRA™-155  
SONET/SDH Payload Extractor/Aligner  
• Maps three DS3 bit streams into a  
STS-3 (STM-1/AU3) frame.  
• Available in a 256-pin, Super Ball Grid  
Array (SBGA) package.  
• Supports industrial temperature range  
(-40°C to 85°C) operation.  
FEATURES  
• Monolithic, SONET/SDH Payload  
• Maps three serial data streams (e.g.,  
Extractor/Aligner for use in STS-1  
Frame Relay, PPP, or Ethernet  
(STM-0/AU3), STS-3 (STM-1/AU3) or  
Payload) into a single serial data  
STS-3c (STM-1/AU4) interface  
BACKPLANE/DEVICE MODES  
• Telecom Byte.  
• Telecom Nibble.  
• Telecom Serial.  
stream into a STS-1 (STM-0/AU3) or  
applications, operating at serial interface  
STS-3c (STM-1/AU4) payload.  
speeds up to 155.52 Mbit/s.  
• Supports line loopback from the line  
• Provides integrated clock recovery and  
side receive stream to the transmit  
clock synthesis to allow a direct interface  
• Datacom Byte.  
stream and diagnostic loopback from a  
to optical modules.  
• Datacom Nibble.  
• Datacom Serial.  
• Datacom T3.  
Telecom ADD bus interface to a  
• Provides termination for SONET Section  
and Line, SDH Regenerator Section and  
Telecom DROP bus interface.  
• Provides a standard 5-signal P1149.1  
Multiplexer Section transport overhead,  
JTAG test port for boundary scan  
and Path overhead of one or three  
APPLICATIONS  
board test purposes.  
STS-1 (STM-0/AU3) paths or a single  
• SONET/SDH Add/Drop Multiplexers  
• SONET/SDH Terminal Multiplexers  
• SONET/SDH Digital Cross-Connects  
• Channelized Routers and Switches  
• Packet Over SONET Router and  
Switches  
• Provides a generic 8-bit  
STS-3c (STM-1/AU4) path.  
• Maps one or three STS-1 (STM-0/AU3)  
payloads or a single STS-3c (STM-1/  
AU4) payload to system timing  
reference, accommodating  
plesiochronous timing offsets between  
the references through pointer  
processing.  
microprocessor bus interface for  
configuration, control, and status  
monitoring.  
• Low power, +5 V, CMOS technology.  
Device has PECL- and TTL-  
compatible inputs and TTL outputs.  
BLOCK DIAGRAM  
3
JTAG  
Test Access  
Port  
Transmit Ring  
Control Port  
Add Bus PRBS  
Generator/  
Monitor  
Transmit  
O/H  
Insert  
Serial  
Control  
Port  
3
DS3 Mapper  
Add Side #1  
DS3 Mapper  
Add Side #2  
3
TRCLK+  
TRCLK-  
DS3 Mapper  
Add Side #3  
Transmit Path O/H  
Processor #1  
Transmit Telecom  
Aligner #1  
TXC  
Transmit  
Line  
Interface  
TXD+  
TXD-  
TBYP  
TATP  
Transmit  
Section O/H  
Processor  
Transmit  
Line O/H  
Processor  
Transmit Path O/H  
Processor #2  
Transmit Telecom  
Aligner #2  
Clock  
Synthesis  
Transmit  
Pointer  
Interpreter #1  
Transmit  
Pointer  
Interpreter #2  
Transmit  
Transmit Path O/H  
Processor #3  
Transmit Telecom  
Aligner #3  
SMODE[2:0]  
SS[34:0]  
Path  
Path  
Path  
Section  
Trace  
Buffer  
Trace Trace Trace  
Buffer Buffer Buffer  
3
#1  
#2  
#3  
RATP  
RBYP  
Pointer  
Interpreter #3  
Receive  
Line  
Interface  
Receive Path O/H  
Processor #1  
Receive Telecom  
Aligner #1  
RXD+  
Clock &  
Data  
Recovery  
Receive  
Section O/H  
Processor  
Receive  
Line O/H  
Processor  
Receive Path O/H  
Processor #2  
Receive Telecom  
Aligner #2  
3
3
RXD-  
Drop Bus PRBS  
Generator/  
Monitor  
Receive Path O/H  
Processor #3  
Receive Telecom  
Aligner #3  
RRCLK+  
RRCLK-  
ALOS+  
ALOS-  
DS3 Mapper  
Drop Side #1  
DS3 Mapper  
Drop Side #2  
3
Transmit  
O/H  
Extract  
DS3 Mapper  
Drop Side #3  
Receive Ring  
Control Port  
Microprocessor  
Interface  
PMC-1970791 (R3)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
Copyright PMC-Sierra, Inc. 2001  

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