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PI74ALVTC16373AX PDF预览

PI74ALVTC16373AX

更新时间: 2024-10-28 14:26:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
10页 342K
描述
Bus Driver, ALVT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.240 INCH, 1.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-48

PI74ALVTC16373AX 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:0.240 INCH, 1.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.91Is Samacsys:N
系列:ALVTJESD-30 代码:R-PDSO-G48
长度:12.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:2.5 ns传播延迟(tpd):4.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

PI74ALVTC16373AX 数据手册

 浏览型号PI74ALVTC16373AX的Datasheet PDF文件第2页浏览型号PI74ALVTC16373AX的Datasheet PDF文件第3页浏览型号PI74ALVTC16373AX的Datasheet PDF文件第4页浏览型号PI74ALVTC16373AX的Datasheet PDF文件第5页浏览型号PI74ALVTC16373AX的Datasheet PDF文件第6页浏览型号PI74ALVTC16373AX的Datasheet PDF文件第7页 
PI74ALVTC16373  
16-Bit Transparent D-Type Latch  
with 3-State Outputs  
ProductFeatures  
ProductDescription  
• PI74ALVTCfamilyisdesignedforlow-voltageoperation,  
VDD =1.8Vto3.6V  
The PI74ALVTC16373 is particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus drivers, and working  
registers. This device can be used as two 8-bit latches or one 16-bit  
latch. When the Latch Enable (LE) input is HIGH, the Q outputs  
follow the (D) inputs. When LE is taken LOW, the Q outputs are  
latched at the levels set up at the D inputs.  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,32/64mA@3.3V  
A buffered Output Enable (OE) input can be used to place the eight  
outputs in either a normal logic state (high or low logic levels) or  
a high-impedance state in which the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the  
increased drive provide the capability to drive bus lines without an  
interface or pullup components. OE does not affect internal  
operations of the latch. Old data can be retained or new data can be  
entered while the ouputs are in the high-impedance state.  
• Uses patented noise reduction circuitry  
• Power-off high-impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packaging(Pb-freeandGreenavailable):  
48-pin240milwideplasticTSSOP(A)  
48-pin173milwideplasticTVSOP(K)  
48-pin300milwideplasticSSOP(V)  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VDD through a pullup resistor; the  
minimumvalueoftheresistorisdeterminedbythecurrent-sinking  
capability of the driver.  
LogicBlockDiagram  
1
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state whenever the data input goes to high-impedance,  
preventing “floating” inputs and eliminating the need for pullup/  
down resistors.  
1OE  
48  
1LE  
C1  
2
1Q1  
47  
1D1  
1D  
To Seven Other Channels  
24  
25  
2OE  
2LE  
C1  
1D  
13  
2Q1  
36  
2D1  
To Seven Other Channels  
PS8355B 05/31/06  
06-0157  
1

PI74ALVTC16373AX 替代型号

型号 品牌 替代类型 描述 数据表
74ALVT16373DGG NEXPERIA

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16-bit transparent D-type latch; 3-stateProduction

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