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PI74ALVTC16373VX PDF预览

PI74ALVTC16373VX

更新时间: 2024-10-29 09:58:43
品牌 Logo 应用领域
百利通 - PERICOM 光电二极管
页数 文件大小 规格书
10页 342K
描述
Bus Driver, ALVT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.300 INCH, 0.635 MM PITCH, PLASTIC, SSOP-48

PI74ALVTC16373VX 数据手册

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PI74ALVTC16373  
16-Bit Transparent D-Type Latch  
with 3-State Outputs  
ProductFeatures  
ProductDescription  
• PI74ALVTCfamilyisdesignedforlow-voltageoperation,  
VDD =1.8Vto3.6V  
The PI74ALVTC16373 is particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus drivers, and working  
registers. This device can be used as two 8-bit latches or one 16-bit  
latch. When the Latch Enable (LE) input is HIGH, the Q outputs  
follow the (D) inputs. When LE is taken LOW, the Q outputs are  
latched at the levels set up at the D inputs.  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,32/64mA@3.3V  
A buffered Output Enable (OE) input can be used to place the eight  
outputs in either a normal logic state (high or low logic levels) or  
a high-impedance state in which the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the  
increased drive provide the capability to drive bus lines without an  
interface or pullup components. OE does not affect internal  
operations of the latch. Old data can be retained or new data can be  
entered while the ouputs are in the high-impedance state.  
• Uses patented noise reduction circuitry  
• Power-off high-impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packaging(Pb-freeandGreenavailable):  
48-pin240milwideplasticTSSOP(A)  
48-pin173milwideplasticTVSOP(K)  
48-pin300milwideplasticSSOP(V)  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VDD through a pullup resistor; the  
minimumvalueoftheresistorisdeterminedbythecurrent-sinking  
capability of the driver.  
LogicBlockDiagram  
1
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state whenever the data input goes to high-impedance,  
preventing “floating” inputs and eliminating the need for pullup/  
down resistors.  
1OE  
48  
1LE  
C1  
2
1Q1  
47  
1D1  
1D  
To Seven Other Channels  
24  
25  
2OE  
2LE  
C1  
1D  
13  
2Q1  
36  
2D1  
To Seven Other Channels  
PS8355B 05/31/06  
06-0157  
1

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