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PI74ALVTC16373KEX PDF预览

PI74ALVTC16373KEX

更新时间: 2024-10-29 10:33:59
品牌 Logo 应用领域
百利通 - PERICOM 驱动光电二极管逻辑集成电路电视
页数 文件大小 规格书
10页 342K
描述
Bus Driver, ALVT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, 0.173 INCH, 1.10 MM HEIGHT, 0.40 MM PITCH, PLASTIC, TVSOP-48

PI74ALVTC16373KEX 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP48,.25,16
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84系列:ALVT
JESD-30 代码:R-PDSO-G48长度:9.7 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:2.5 ns
传播延迟(tpd):4.5 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.8 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

PI74ALVTC16373KEX 数据手册

 浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第2页浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第3页浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第4页浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第5页浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第6页浏览型号PI74ALVTC16373KEX的Datasheet PDF文件第7页 
PI74ALVTC16373  
16-Bit Transparent D-Type Latch  
with 3-State Outputs  
ProductFeatures  
ProductDescription  
• PI74ALVTCfamilyisdesignedforlow-voltageoperation,  
VDD =1.8Vto3.6V  
The PI74ALVTC16373 is particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus drivers, and working  
registers. This device can be used as two 8-bit latches or one 16-bit  
latch. When the Latch Enable (LE) input is HIGH, the Q outputs  
follow the (D) inputs. When LE is taken LOW, the Q outputs are  
latched at the levels set up at the D inputs.  
• Supports Live Insertion  
• 3.6V I/O Tolerant Inputs and Outputs  
• Bus Hold  
• HighDrive,32/64mA@3.3V  
A buffered Output Enable (OE) input can be used to place the eight  
outputs in either a normal logic state (high or low logic levels) or  
a high-impedance state in which the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the  
increased drive provide the capability to drive bus lines without an  
interface or pullup components. OE does not affect internal  
operations of the latch. Old data can be retained or new data can be  
entered while the ouputs are in the high-impedance state.  
• Uses patented noise reduction circuitry  
• Power-off high-impedance inputs and outputs  
• Industrial operation at –40°C to +85°C  
• Packaging(Pb-freeandGreenavailable):  
48-pin240milwideplasticTSSOP(A)  
48-pin173milwideplasticTVSOP(K)  
48-pin300milwideplasticSSOP(V)  
To ensure the high-impedance state during power up or power  
down, OE should be tied to VDD through a pullup resistor; the  
minimumvalueoftheresistorisdeterminedbythecurrent-sinking  
capability of the driver.  
LogicBlockDiagram  
1
The family offers both I/O Tolerant, which allows it to operate in  
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data  
input’s last state whenever the data input goes to high-impedance,  
preventing “floating” inputs and eliminating the need for pullup/  
down resistors.  
1OE  
48  
1LE  
C1  
2
1Q1  
47  
1D1  
1D  
To Seven Other Channels  
24  
25  
2OE  
2LE  
C1  
1D  
13  
2Q1  
36  
2D1  
To Seven Other Channels  
PS8355B 05/31/06  
06-0157  
1

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