Datasheet > PI74ALVCH16841

PI74ALVCH16841

更新时间： 2024-10-26 23:27:39

品牌	Logo	应用领域
其他 - ETC		锁存器
页数	文件大小	规格书
5页	275K
描述
Logic \| 20-Bit Bus Interface D-Type Latch

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中文翻译

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数据手册

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PI74ALVCH16841 数据手册

PI74ALVCH16841

20-Bit Bus-Interface D-Type Latch

with 3-STATE Outputs

Product Features

ProductDescription

Pericom Semiconductors PI74ALVCH series of logic circuits are

producedintheCompanysadvanced0.5micronCMOStechnology,

achieving industry leading speed.

• PI74ALVCH16841 is designed for low voltage operation

• V = 2.3V to 3.6V

• Hysteresis on all inputs

ThePI74ALVCH16841,a20-bitbus-interfaceD-typelatch designed

• Typical V

(Output Ground Bounce)

OLP

for2.3Vto3.6VV operation.

< 0.8V atV = 3.3V, T = 25°C

ThePI74ALVCH16841features3-stateoutputsdesignedspecifically

for driving highly capacitive or relatively low-impedance loads.

It is particularly suitable for implementing buffer registers,

unidirectional bus drivers, and working registers.

• Typical V

(Output V Undershoot)

OHV

< 2.0V atV = 3.3V, T = 25°C

• Bus Hold retains last active bus state during 3-STATE,

eliminating the need for external pullup resistors

• Industrial operation at 40°C to +85°C

• Packages available:

The PI74ALVCH16841 can be used as two 10-bit latches or one

20-bit latch (transparent D-type). The device has non-inverting

Data (D) inputs and provides true data at its outputs. While the

Latch Enable (1LE or 2LE) input is HIGH, the Q outputs of the

corresponding 10-bit latch follow the D inputs. When LE is taken

LOW, the Q outputs are latched at the levels set up at the D inputs.

56-pin 240 mil wide plastic TSSOP (A)

56-pin 300 mil wide plastic SSOP (V)

A buffered Output Enable (1OE or 2OE) input can be used to place

theoutputsofthecorresponding10-bitlatchineitheranormallogic

state (high or low logic levels) or a high-impedance state. In that

state, outputs neither load nor drive the bus lines significantly.

LogicBlockDiagram

TheOutputEnable(OE)inputdoesnotaffecttheinternaloperation

of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

1OE

1LE

To ensure the high-impedance state during power up or power

down, OE should be tied to V through a pullup resistor; the

1Q1

minimumvalue of the resistor is determined by the current-sinking

capability of the driver.

1D1

Active bus-hold circuitry is provided to hold unused or floating

data inputs at a valid logic level.

TO NINE OTHER CHANNELS

2OE

2LE

2Q1

2D1

TO NINE OTHER CHANNELS

PS8182A

11/06/00

12 3 4 5

中文翻译

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与PI74ALVCH16841相关器件

型号	品牌	获取价格	描述	数据表
PI74ALVCH16841A	ETC	获取价格	10-Bit D-Type Latch
PI74ALVCH16841AE	PERICOM	获取价格	Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLAS
PI74ALVCH16841AEX	PERICOM	获取价格	Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.240 INCH, PLAS
PI74ALVCH16841V	ETC	获取价格	10-Bit D-Type Latch
PI74ALVCH16841VEX	PERICOM	获取价格	Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLAS
PI74ALVCH16841VX	PERICOM	获取价格	Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56, 0.300 INCH, PLAS
PI74ALVCH16863	ETC	获取价格	Logic \| 18-Bit Transceiver
PI74ALVCH16863A	ETC	获取价格	9-Bit Bus Transceiver
PI74ALVCH16863AE	PERICOM	获取价格	Bus Transceiver, ALVC/VCX/A Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.240 INCH,
PI74ALVCH16863AEX	PERICOM	获取价格	Bus Transceiver, ALVC/VCX/A Series, 2-Func, 9-Bit, True Output, CMOS, PDSO56, 0.240 INCH,

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