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PI74ALVCH16841V PDF预览

PI74ALVCH16841V

更新时间: 2024-10-26 23:27:39
品牌 Logo 应用领域
其他 - ETC 锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
5页 264K
描述
10-Bit D-Type Latch

PI74ALVCH16841V 数据手册

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PI74ALVCH16841  
20-Bit Bus-Interface D-Type Latch  
with 3-State Outputs  
Product Features  
ProductDescription  
Pericom Semiconductor’s PI74ALVCH series of logic circuits are  
produced using the Company’s advanced 0.5 micron CMOS  
technology, achieving industry leading speed.  
PI74ALVCH16841 is designed for low voltage operation  
V = 2.3V to 3.6V  
CC  
Hysteresis on all inputs  
ThePI74ALVCH16841,a20-bitbus-interfaceD-typelatch designed  
Typical V  
(Output Ground Bounce)  
OLP  
for2.3Vto3.6VV operation.  
CC  
< 0.8V atV = 3.3V, T = 25°C  
CC  
A
ThePI74ALVCH16841features3-stateoutputsdesignedspecifically  
for driving highly capacitive or relatively low-impedance loads.  
It is particularly suitable for implementing buffer registers,  
unidirectional bus drivers, and working registers.  
Typical V  
(Output V Undershoot)  
OH  
OHV  
< 2.0V atV = 3.3V, T = 25°C  
CC  
A
Bus Hold retains last active bus state during 3-State,  
eliminating the need for external pullup resistors  
Industrial operation at –40°C to +85°C  
Packages available:  
The PI74ALVCH16841 can be used as two 10-bit latches or one  
20-bit latch (transparent D-type). The device has non-inverting  
Data (D) inputs and provides true data at its outputs. While the  
Latch Enable (1LE or 2LE) input is HIGH, the Q outputs of the  
corresponding 10-bit latch follow the D inputs. When LE is taken  
LOW, the Q outputs are latched at the levels set up at the D inputs.  
– 56-pin 240 mil wide plastic TSSOP (A)  
– 56-pin 300 mil wide plastic SSOP (V)  
A buffered Output Enable (1OE or 2OE) input can be used to place  
theoutputsofthecorresponding10-bitlatchineitheranormallogic  
state (high or low logic levels) or a high-impedance state. In that  
state, outputs neither load nor drive the bus lines significantly.  
LogicBlockDiagram  
TheOutputEnable(OE)inputdoesnotaffecttheinternaloperation  
of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
1
1OE  
56  
1LE  
To ensure the high-impedance state during power up or power  
C1  
2
down, OE should be tied to V through a pullup resistor; the  
CC  
1Q1  
55  
minimumvalue of the resistor is determined by the current-sinking  
capability of the driver.  
1D1  
1D  
Active bus-hold circuitry is provided to hold unused or floating  
data inputs at a valid logic level.  
TO NINE OTHER CHANNELS  
28  
29  
2OE  
2LE  
C1  
1D  
15  
2Q1  
42  
2D1  
TO NINE OTHER CHANNELS  
PS8182A  
11/06/00  
1

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