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PI6CV847LE PDF预览

PI6CV847LE

更新时间: 2024-11-29 20:37:47
品牌 Logo 应用领域
美台 - DIODES 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 375K
描述
PLL Based Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, GREEN, TSSOP-24

PI6CV847LE 数据手册

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PI6CV847  
200MHz PLL Clock Driver  
Features  
Description  
• PLLclockdistributionoptimizedforSSTL_2  
ThePI6CV847PLLClockBufferisdesignedfor2.5V  
and2.5V  
DDQ  
• Distributes one differential clock input pair to five differential  
clock output pairs.  
AV operation and differential data input and output levels. The  
DD  
deviceisazerodelaybufferthatdistributesadifferentialclockinput  
pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4],  
Y[0:4]) and one differential pair feedback clock outputs (FBOUT,  
FBOUT).Theclockoutputsarecontrolledbytheinputclocks(CLK,  
CLK),thefeedbackclocks(FBIN,FBIN),andtheAnalogPowerinput  
• Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2  
• Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2  
• Externalfeedbackpins(FBIN,FBIN)areusedto  
synchronize the outputs to the input clocks.  
(AV ). WhentheAV isstrappedlow, thePLListurnedoffand  
DD  
DD  
• Operates at AV = 2.5V for core circuit and internal PLL,  
DD  
bypassed for test purposes.  
and V = 2.5V for differential output drivers  
DD  
ThePI6CV847isabletotrackSpreadSpectrumClockingtoreduce  
EMI.  
• Packaging(Pb-free&Greenavailable):  
-24-pinTSSOP(L24)  
PinConfiguration  
BlockDiagram  
GND  
Y0  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Y4  
Y0  
2
Y4  
Y0  
Y1  
Y0  
3
Y3  
CLK  
CLK  
GND  
VDD  
CLKIN  
CLKIN  
AVDD  
AGND  
Y1  
4
Y3  
Y1  
Y2  
5
VDD  
FBIN  
FBIN  
FBOUT  
FBOUT  
Y2  
PLL  
FBIN  
24-Pin  
L
Y2  
Y3  
6
FBIN  
7
Y3  
Y4  
8
9
Y4  
Logic  
and  
Test Ciruit  
10  
11  
12  
FBOUT  
FBOUT  
Y1  
Y2  
AV  
DD  
VDD  
GND  
PS8764D  
10/02/06  
06-0280  
1

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