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PI6CV857LKE PDF预览

PI6CV857LKE

更新时间: 2024-11-29 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器动态存储器双倍数据速率
页数 文件大小 规格书
9页 342K
描述
PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173 INCH, PLASTIC, TVSOP-48

PI6CV857LKE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP,
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.67系列:6C
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G48
长度:9.7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:48实输出次数:10
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:170 MHz
Base Number Matches:1

PI6CV857LKE 数据手册

 浏览型号PI6CV857LKE的Datasheet PDF文件第2页浏览型号PI6CV857LKE的Datasheet PDF文件第3页浏览型号PI6CV857LKE的Datasheet PDF文件第4页浏览型号PI6CV857LKE的Datasheet PDF文件第5页浏览型号PI6CV857LKE的Datasheet PDF文件第6页浏览型号PI6CV857LKE的Datasheet PDF文件第7页 
PI6CV857L  
PLL Clock Driver for  
2.5V DDR-SDRAM Memory  
ProductFeatures  
ProductDescription  
• PLL clock distribution optimized for Double Data Rate  
SDRAMapplications.  
PI6CV857LPLLclockdeviceisdevelopedforregisteredDDRDIMM  
applicationsThisPLLClockBufferisdesignedfor2.5V and2.5V  
DDQ  
• Distributes one differential clock input pair to ten differential  
clock output pairs.  
AV  
operation and differential data input and output levels.  
DD  
PackageoptionsincludeplasticThinShrinkSmall-OutlinePackage  
(TSSOP).The device is a zero delay buffer that distributes a differ-  
ential clock input pair (CLK, CLK) to ten differential pairs of clock  
outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock  
outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe  
inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V  
LVCMOSinput(PWRDWN)andtheAnalogPowerinput(AV ).  
When input PWRDWN is low while power is applied, the input  
receiversaredisabled,thePLListurnedoffandthedifferentialclock  
• Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2  
• Input PWRDWN: LVCMOS  
• Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2  
• Externalfeedbackpins(FBIN,FBIN)areusedto  
synchronize the outputs to the clock input.  
DD  
• Operates at AV = 2.5V for core circuit and internal PLL,  
DD  
and V  
= 2.5V for differential output drivers  
DDQ  
• AvailablePackages:Plastic48-pinTSSOP  
outputs are 3-stated. When the AV is strapped low, the PLL is  
DD  
turned off and bypassed for test purposes.  
When the input frequency falls below a suggested detection fre-  
quency that is below the operating frequency of the PLL, the device  
willenteralowpowermode.Aninputfrequencydetectioncircuitwill  
detectthelowfrequencyconditionandperformthesamelowpower  
features as when the PWRDWN input is low.  
ThePLLinthePI6CV857Lclockdriverusestheinputclocks(CLK,  
CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-  
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).  
ThePI6CV857LisalsoabletotrackSpreadSpectrumClockingfor  
reducedEMI.  
BlockDiagram/PinConfiguration  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
Y0  
GND  
Y5  
Y5  
V
3
4
Y0  
V
D D Q  
Y1  
D D Q  
5
6
Y6  
Y1  
Y6  
GND  
7
GND  
GND  
Y2  
8
9
GND  
Y7  
Y7  
V
48-Pin  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Y2  
V
V
D D Q  
D D Q  
D D Q  
CLK  
CLK  
D D Q  
P W R DW N  
FBIN  
FBIN  
V
V
D D Q  
AV  
FBOUT  
FBOUT  
D D  
AGND  
GND  
Y3  
GND  
Y8  
Y8  
Y3  
V
V
D D Q  
D D Q  
Y4  
Y4  
Y9  
Y9  
GND  
GND  
PS8543  
06/11/01  
1

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