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PI6CVF857ZD PDF预览

PI6CVF857ZD

更新时间: 2024-11-29 19:43:55
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
14页 298K
描述
PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), TQFN-40

PI6CVF857ZD 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC40,.24SQ,20针数:40
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.89
系列:6C输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N40JESD-609代码:e0
长度:6 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A功能数量:1
反相输出次数:端子数量:40
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC40,.24SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):235
电源:2.5 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.7 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
最小 fmax:170 MHzBase Number Matches:1

PI6CVF857ZD 数据手册

 浏览型号PI6CVF857ZD的Datasheet PDF文件第2页浏览型号PI6CVF857ZD的Datasheet PDF文件第3页浏览型号PI6CVF857ZD的Datasheet PDF文件第4页浏览型号PI6CVF857ZD的Datasheet PDF文件第5页浏览型号PI6CVF857ZD的Datasheet PDF文件第6页浏览型号PI6CVF857ZD的Datasheet PDF文件第7页 
PI6CVF857  
1:10 PLL Clock Driver for  
2.5V DDR-SDRAM Memory  
ProductFeatures  
ProductDescription  
• Operating Frequency up to 220 MHz for PC3200 Registered  
PI6CVF857PLLclockdeviceisdevelopedforregisteredDDRDIMM  
applications. The device is a zero-delay buffer that distributes a  
differential clock input pair (CLK, CLK) to ten differential pairs of  
clockoutputs(Y[0:9],Y[0:9]),andonedifferentialpairfeedbackclock  
outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe  
inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V  
DIMM applications  
• Distributes one differential clock input pair to ten differential  
clock output pairs  
• Inputs(CLK,CLK)and(FBIN,FBIN)  
• Input PWRDWN: LVCMOS  
• Outputs (Yx,Yx),(FBOUT,FBOUT)  
• Externalfeedbackpins(FBIN,FBIN)areusedto  
synchronize the outputs to the clock input  
• Operatesat2.5VforPC1600,PC2100,PC2700,  
and2.6VforPC3200  
LVCMOSinput(PWRDWN),andtheAnalogPowerinput(AV ).  
DD  
When input PWRDWN is low while power is applied, the input  
receiversaredisabled,thePLListurnedoff,andthedifferentialclock  
outputs are 3-stated. When the AV is strapped low, the PLL is  
DD  
turned off and bypassed for test purposes.  
When the input frequency falls below a suggested detection fre-  
quency that is below the operating frequency of the PLL, the device  
willenteralowpowermode.Aninputfrequencydetectioncircuitwill  
detectthelowfrequencyconditionandperformthesamelowpower  
features as when the PWRDWN input is low.  
ThePLLinthePI6CVF857clockdriverusestheinputclocks(CLK,  
CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-  
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).  
The PI6CVF857 is also able to track Spread Spectrum Clocking for  
reducedEMI.  
• Packaging (Pb-free & Green available, select packages):  
48-pinTSSOP  
40-pinTQFN  
56-ballVFBGA  
BlockDiagram  
Y0  
Y0  
Y1  
CLK  
Y1  
CLK  
Y2  
PLL  
FBIN  
FBIN  
Y2  
Y3  
Y3  
Y4  
Y4  
Y5  
Y5  
Y6  
Powerdown  
and Test  
Logic  
PWRDWN  
Y6  
Y7  
AV  
DD  
Y7  
Y8  
Y8  
Y9  
Y9  
FBOUT  
FBOUT  
PS8683B  
10/17/03  
1

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