Datasheet > PI6CXG06F62A

PI6CXG06F62A

更新时间： 2024-11-30 01:15:47

品牌	Logo	应用领域
百利通 - PERICOM		/
页数	文件大小	规格书
2页	580K
描述
FlexOut Ultra Low Jitter Clock Generator

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中文翻译

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数据手册

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PI6CXG06F62A 数据手册

PI6CXG06F62a

FlexOut Ultra Low Jitter Clock Generator

Features

Description

ꢀÎUltra low jitter 156.25MHz clock generator <0.15ps max (12k

e PI6CXG06F62a is part of Pericom's FlexOut clock genera-

tor family. FlexOut generators combine a low jitter high per-

formance clock generator along with fanout capabilities. It also

integrates a unique feature with user conﬁgurable output signal-

ing standards on per bank basis which provide great ﬂexibility

to users. is device is ideal for systems that need to distribute

low jitter clock signals to multiple destinations.

to 20MHz) in LVPECL and LVDS conﬁguration

ꢀÎ6 diﬀerential outputs with 2 banks

ꢀÎUser conﬁgurable output signaling standard for each bank:

LVDS or LVPECL or HCSL

ꢀÎSeparate supply voltages for customizable output levels

ꢀÎLow skew between outputs within banks (<40ps)

ꢀÎ2.5V / 3.3V power supply

Applications

ꢀÎNetworking systems including switches and routers

ꢀÎIndustrial temperature support

ꢀÎLQFP-48 package

ꢀÎHigh frequency backplane based computing and telecom

platforms

Block Diagram

LVPECL Phase Noise Plot

OPMODEA[1:0]

QA[0:2]

OPMODEB[1:0]

Embedded

Clock Source

QB[0:2]

IREF

PI6CXG06F62a Data Brief Rev A

08/15/14

中文翻译

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