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PI6LC4840 PDF预览

PI6LC4840

更新时间: 2024-12-01 14:55:27
品牌 Logo 应用领域
美台 - DIODES /
页数 文件大小 规格书
10页 771K
描述
CMOS & LVDS Ethernet Clock Generator

PI6LC4840 数据手册

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PI6LC4840  
Crystal to LVDS/LVCMOS Frequency Synthesizer  
Features  
Description  
Î 3.3V supply voltage 5%  
Î ree banks of outputs:  
e PI6LC4840 is an LC VCO based low phase noise design in-  
tended for the most demanding Ethernet applications. Common  
Ethernet frequencies of 25MHz and 125MHz are supported,  
with the 125Mhz having both LVDS and LVCMOS outputs for  
maximum flexibility. One 25Mhz LVCMOS non-PLL output is  
also available.  
à Bank A: 3 25/50MHz pin selectable LVCMOS outputs  
à Bank B: 3 125MHz LVCMOS outputs  
à Bank C: 3 125MHz LVDS outputs  
Î 1 25MHz LVCMOS reference clock output (no PLL)  
Î 25MHz crystal input (SaRonix-eCera P/N FL2500029)  
Î Low 1ps max 12k-20MHz integrated phase noise design (for  
125MHz CMOS and LVDS outputs)  
Î Industrial temperature -40°C to 85°C  
Î Package (Pb-free & Green)  
à 32-contact 5x5mm TQFN (ZH)  
Block Diagram  
Mode_1 = Pull-up  
Mode_0,2 = Pull-down  
3
Control  
Mode [2:0]  
Logic  
VDDO_QA  
LVCMOS  
- 25MHz or 50MHz  
QA0  
QA1  
QA2  
÷20  
or ÷10  
SaRonix-eCera FL2500029  
25MHz  
X1  
Phase  
Detector  
OSC  
VCO  
VDDO_QB  
X2  
CMOS - 125MHz  
QB0  
QB1  
QB2  
÷4  
\M  
VDDO_QC  
LVDS 125MHz  
QC0+  
QC0-  
QC1+  
QC1-  
÷4  
QC2+  
QC2-  
Pull-down  
MR  
LVCMOS - 25MHz  
REF_Out  
www.pericom.com  
PS9076  
01/03/11  
10-0249  
1

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