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PI6LC4820 PDF预览

PI6LC4820

更新时间: 2024-12-01 01:22:51
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
13页 1215K
描述
HiFlex Ethernet Network Clock Generator

PI6LC4820 数据手册

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PI6LC4820  
TM  
HiFlex Ethernet Network Clock Generator  
Features  
Description  
Î3.3V supply voltage  
ÎCrystal input: 25 MHz  
ÎDifferential input: 25MHz, 156.25 MHz  
ÎOutput frequencies of 312.5, 156.25, 125MHz supported  
Î9 LVPECL or LVDS bank selectable outputs  
e PI6LC4820 is an LC VCO based low phase noise design  
intended for 10GbE applications. Typical 10GbE usage assumes  
a 25Mhz crystal input, while the PLL loop is used to generate  
the 156.25MHz outputs. An additional buffered crystal oscilla-  
tor output is provided to serve as a low noise reference for other  
circuitry.  
ÎLow 1ps max integrated phase noise design  
For Ethernet applications other than 10GbE, programmable  
dividers allow for simultaneous output of 312.5, 156.25, and  
125MHz.  
(12kHz to 20MHz)  
ÎOptional xtal or clock input selection  
ÎPLL Bypass mode for test  
ÎPower supply noise rejection: -50 dBc typical @ 156.25 MHz  
ÎPackaging (Pb-free & Green): 48-lead 7×7mm TQFN  
Pin Configuration  
48 47 46 45 44 43 42 41 40 39 38 37  
1
V
DD_QA  
36  
FS0  
2
QA0+  
QA0-  
QA1+  
QA1-  
35  
34  
33  
32  
X1  
3
X2  
4
V
DD_OSC  
5
IN_SEL  
6
QA2+  
QA2-  
QA3+  
QA3-  
QA4+  
31  
30  
29  
28  
27  
26  
25  
PLL_BYPS  
GND  
GND  
7
8
FS1  
9
QC_Mode  
10  
11  
12  
V
DDA  
GND  
QA4-  
V
V
DD_PLL  
DD_QA  
13 14 15 16 17 18 19 20 21 22 23 24  
PI6LC4820 Rev D  
11/13/13  
13-0167  
1

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