Datasheet > PI6LC4831A

PI6LC4831A

更新时间： 2024-12-01 14:55:55

品牌	Logo	应用领域
美台 - DIODES		/
页数	文件大小	规格书
14页	839K
描述
Crystal to Differential HCSL/LVCMOS Frequency Synthesizer

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中文翻译

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PI6LC4831A 数据手册

PI6LC4831A

Crystal to Diﬀerential HCSL/LVCMOS Frequency Synthesizer

Features

Description

Î 3.3V ± 5% Supply Voltage

e PI6LC4831A clock generator supports networking systems

requiring 25MHz for ethernet and 100MHz for PCIe applica-

Î Industrial temperature -40°C to 85°C

Î Uses 25MHz xtal

tions. is novel part includes both a low phase noise VCO and

a traditional VCO which supports spread spectrum applications.

Twelve copies of the 25MHz reference clock are provided, evenly

divided between true and complimentary outputs to minimize

EMI and di/dt. e low phase noise LC VCO drives 2 HCSL out-

puts and the 24MHz LVCMOS outputs. e Spread spectrum

ring oscillator drives a 100MHz or 200MHz selectable HCSL out-

put. I²C control is included for on-board frequency and spread

spectrum functionality changes.

Î Two low jitter PCIe 100MHz outputs

Î One 100/200MHz selectable HCSL output with spread

spectrum support

Î 12 LVCMOS 25MHz reference clock outputs

Î Two LVCMOS 24MHz outputs

Î I²C Interface

Î Packaging (Pb-free & Green available):

à 8mm × 8mm 56-pinTQFN

Pin Conﬁguration (56-Pin TQFN)

Block Diagram

LVCMOS - 25MHz

Qa_Ref

a= 0, 2, 4, 6, 8, 10

nQb_Ret

b= 1, 3, 5, 7, 9, 11

25MHz

PLL 1

Q0A_PLL1+

Q0A_PLL1-

OSC

Phase

Detector

LC VCO

2.4GHz

÷4

÷6

Q1A_PLL1+

Q1A_PLL1-

5655 54 53 52 51 5049 48 47 46 45 44 43

VDD

VDDO_24MHz

Q3B_PLL1

GND

nQ2B_PLL1

VDDO_24MHz

VDDA1

GND

VDDA2

IREF

Q0A_PLL1+

Q0A_PLL1-

Q1A_PLL1+

Q1A_PLL1-

÷96

LVCMOS - 24MHz

nQ2B_PLL1

÷25

IREF

Q3B_PLL1

GND

PI6LC4831A

VDD

PLL2

HCSL - 100MHz or 200MHz

RESET

ADDR_SEL

SDATA

SCLK

Phase

Detector

Ring VCO

1.8 - 2.2GHz

Q0_PLL2+

Q0_PLL2-

÷10,

÷5

÷2

GND

Q0_PLL2-

Q0_PLL2+

VDD

72 - 88

(80 defult)

Controlled by

M4:M0

VDD

1516 17 18 19 20 2122 23 24 25 26 2728

SCLK

Spread

I²C

Control

Block

Spectrum

SDATA

Bypass

ADDR_SEL

RESET

Output Enable

All trademarks are property of their respective owners.

www.pericom.com

P-0.1

07/18/11

11-0086

12 3 4 5 6 7...14

中文翻译

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