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PI6CVF857 PDF预览

PI6CVF857

更新时间: 2024-11-28 22:28:55
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器动态存储器双倍数据速率
页数 文件大小 规格书
14页 303K
描述
1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory

PI6CVF857 数据手册

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PI6CVF857  
1:10 PLL Clock Driver for  
2.5V DDR-SDRAM Memory  
ProductFeatures  
ProductDescription  
• Operating Frequency up to 220 MHz for PC3200 Registered  
PI6CVF857PLLclockdeviceisdevelopedforregisteredDDRDIMM  
applications. The device is a zero-delay buffer that distributes a  
differential clock input pair (CLK, CLK) to ten differential pairs of  
clockoutputs(Y[0:9],Y[0:9]),andonedifferentialpairfeedbackclock  
outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe  
inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V  
DIMM applications  
• Distributes one differential clock input pair to ten differential  
clock output pairs  
• Inputs(CLK,CLK)and(FBIN,FBIN)  
• Input PWRDWN: LVCMOS  
• Outputs (Yx,Yx),(FBOUT,FBOUT)  
• Externalfeedbackpins(FBIN,FBIN)areusedto  
synchronize the outputs to the clock input  
• Operatesat2.5VforPC1600,PC2100,PC2700,  
and2.6VforPC3200  
LVCMOSinput(PWRDWN),andtheAnalogPowerinput(AV ).  
DD  
When input PWRDWN is low while power is applied, the input  
receiversaredisabled,thePLListurnedoff,andthedifferentialclock  
outputs are 3-stated. When the AV is strapped low, the PLL is  
DD  
turned off and bypassed for test purposes.  
When the input frequency falls below a suggested detection fre-  
quency that is below the operating frequency of the PLL, the device  
willenteralowpowermode.Aninputfrequencydetectioncircuitwill  
detectthelowfrequencyconditionandperformthesamelowpower  
features as when the PWRDWN input is low.  
ThePLLinthePI6CVF857clockdriverusestheinputclocks(CLK,  
CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-  
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).  
The PI6CVF857 is also able to track Spread Spectrum Clocking for  
reducedEMI.  
• Packaging (Pb-free & Green available, select packages):  
48-pinTSSOP  
40-pinTQFN  
56-ballVFBGA  
BlockDiagram  
Y0  
Y0  
Y1  
CLK  
Y1  
CLK  
Y2  
PLL  
FBIN  
FBIN  
Y2  
Y3  
Y3  
Y4  
Y4  
Y5  
Y5  
Y6  
Powerdown  
and Test  
Logic  
PWRDWN  
Y6  
Y7  
AV  
DD  
Y7  
Y8  
Y8  
Y9  
Y9  
FBOUT  
FBOUT  
PS8683B  
10/17/03  
1

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