PI6CV857LAE

更新时间： 2024-11-29 12:59:19

品牌	Logo	应用领域
百利通 - PERICOM		时钟驱动器动态存储器双倍数据速率
页数	文件大小	规格书
9页	342K
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中文翻译

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数据手册
替代型号

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PI6CV857LAE 数据手册

PI6CV857L

PLL Clock Driver for

2.5V DDR-SDRAM Memory

ProductFeatures

ProductDescription

PLL clock distribution optimized for Double Data Rate

SDRAMapplications.

PI6CV857LPLLclockdeviceisdevelopedforregisteredDDRDIMM

applicationsThisPLLClockBufferisdesignedfor2.5V and2.5V

DDQ

Distributes one differential clock input pair to ten differential

clock output pairs.

operation and differential data input and output levels.

PackageoptionsincludeplasticThinShrinkSmall-OutlinePackage

(TSSOP).The device is a zero delay buffer that distributes a differ-

ential clock input pair (CLK, CLK) to ten differential pairs of clock

outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock

outputs(FBOUT,FBOUT). Theclockoutputsarecontrolledbythe

inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V

LVCMOSinput(PWRDWN)andtheAnalogPowerinput(AV ).

When input PWRDWN is low while power is applied, the input

receiversaredisabled,thePLListurnedoffandthedifferentialclock

Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

Input PWRDWN: LVCMOS

Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

Externalfeedbackpins(FBIN,FBIN)areusedto

synchronize the outputs to the clock input.

Operates at AV = 2.5V for core circuit and internal PLL,

and V

= 2.5V for differential output drivers

DDQ

AvailablePackages:Plastic48-pinTSSOP

outputs are 3-stated. When the AV is strapped low, the PLL is

turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

willenteralowpowermode.Aninputfrequencydetectioncircuitwill

detectthelowfrequencyconditionandperformthesamelowpower

features as when the PWRDWN input is low.

ThePLLinthePI6CV857Lclockdriverusestheinputclocks(CLK,

CLK)andthefeedbackclocks(FBIN,FBIN)toprovidehigh-perfor-

mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).

ThePI6CV857LisalsoabletotrackSpreadSpectrumClockingfor

reducedEMI.

BlockDiagram/PinConfiguration

GND

D D Q

GND

48-Pin

D D Q

CLK

D D Q

P W R DW N

FBIN

D D Q

FBOUT

D D

AGND

GND

D D Q

GND

PS8543

06/11/01

12 3 4 5 6 7...9

中文翻译

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PI6CV857LAE 替代型号

型号	品牌	替代类型	描述	数据表
CDCV857DGGR	TI	类似代替	2.5-V PHASE LOCK LOOP CLOCK DRIVER
CDCVF857DGGR	TI	功能相似	2.5-V PHASE-LOCK LOOP CLOCK DRIVER
CDCVF857DGG	TI	功能相似	2.5-V PHASE-LOCK LOOP CLOCK DRIVER

与PI6CV857LAE相关器件

型号	品牌	获取价格	描述	数据表
PI6CV857LAEX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
PI6CV857LAX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240
PI6CV857LK	PERICOM	获取价格	暂无描述
PI6CV857LKE	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173
PI6CV857LKX	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.173
PI6CVF857	PERICOM	获取价格	1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
PI6CVF857A	PERICOM	获取价格	1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
PI6CVF857AE	PERICOM	获取价格	1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
PI6CVF857NF	PERICOM	获取价格	1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory
PI6CVF857NFE	PERICOM	获取价格	PLL Based Clock Driver, 6C Series, 10 True Output(s), 0 Inverted Output(s), PBGA56, VFBGA-

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