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PI6C39912-5 PDF预览

PI6C39912-5

更新时间: 2024-09-30 15:47:51
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
12页 504K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

PI6C39912-5 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.92
系列:6C输入调节:STANDARD
JESD-30 代码:R-PQCC-J32JESD-609代码:e0
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.7 ns最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:J BEND
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
最小 fmax:133 MHzBase Number Matches:1

PI6C39912-5 数据手册

 浏览型号PI6C39912-5的Datasheet PDF文件第2页浏览型号PI6C39912-5的Datasheet PDF文件第3页浏览型号PI6C39912-5的Datasheet PDF文件第4页浏览型号PI6C39912-5的Datasheet PDF文件第5页浏览型号PI6C39912-5的Datasheet PDF文件第6页浏览型号PI6C39912-5的Datasheet PDF文件第7页 
ADVANCE INFORMATION  
PI6C39911/PI6C39912  
3.3V High Speed LVTTL or Balanced Output  
Programmable Skew Clock Buffer-SuperClock  
Features  
Description  
• All output pair skew <100ps typical (250 Max.)  
• 3.75 MHz to 133 MHz output operation  
• User-selectable output functions  
— Selectable skew to 18ns  
ThePI6C39911andPI6C39912offerselectablecontroloversystem  
clock functions. These multiple-output clock drivers provide the  
systemintegratorwithfunctionsnecessarytooptimizethetimingof  
high-performance computer systems. Eight individual drivers, ar-  
ranged as four pairs of user-controllable outputs, can each drive  
terminated transmission lines with impedances as low as 50 Ohm  
whiledeliveringminimalandspecifiedoutputskewsandfull-swing  
logiclevels.  
— Inverted and Non-Inverted  
— Operation at ½ and ¼ input frequency  
— Operation at 2X and 4X input frequency  
(input as low as 3.75 MHz)  
Each output can be hardwired to one of nine delay or function  
configurations. Delay increments of 0.7ns to 1.5ns are determined  
by the operating frequency with outputs able to skew up to ±6 time  
units from their nominal “zero” skew position. The completely  
integrated PLL allows external load and transmission line delay  
effects to be canceled. The user can create output-to-output delays  
of up to ±12 time units.  
• Zero input-to-output delay  
• 50% duty-cycle outputs  
• LVTTL outputs drive 50 Ohm terminated lines  
• Operates from a single 3.3V supply  
• Low operating current  
Divide-by-twoanddivide-by-fouroutputfunctionsareprovidedfor  
additional flexibility in designing complex clock systems. When  
combinedwiththeinternalPLL,thesedividefunctionsallowdistri-  
butionofalow-frequencyclockthatcanbemultipliedbytwoorfour  
at the clock destination. This facility minimizes clock distribution  
difficulty while allowing maximum system user-clock speed and  
flexibility.  
• 32-pinPLCCpackage  
• Jitter < 200ps peak-to-peak (< 25ps RMS)  
• AvailableinLVTTL(PI6C39911)orBalanced(PI6C39912)  
• PI6C39911isapin-to-pincompatiblewithCY7B9911V  
LogicBlockDiagram  
PinConfiguration  
Test  
Phase  
Freq.  
DET  
VCO and  
Time Unit  
Generator  
FB  
1Q0  
1Q1  
Filter  
REF  
4
3
2
1
32 31 30  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
3F1  
4F0  
4F1  
2F0  
GND  
1F1  
1F0  
6
4Q0  
4Q1  
7
4F0  
4F1  
8
V
CCQ  
32-pin PLCC  
Select Inputs  
(three level)  
9
V
V
CCN  
4Q1  
CCN  
Skew  
10  
11  
12  
13  
3Q0  
3Q1  
1Q0  
1Q1  
GND  
GND  
3F0  
3F1  
4Q0  
Select  
GND  
GND  
2Q0  
2Q1  
2F0  
2F1  
14 15 16 17 18 19 20  
Matrix  
1Q0  
1Q1  
1F0  
1F1  
PSXXXX  
05/10/00  
1

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