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PI6C3993-5AC PDF预览

PI6C3993-5AC

更新时间: 2024-11-18 15:47:51
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
13页 226K
描述
PLL Based Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP100, PLASTIC, TQFP-100

PI6C3993-5AC 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:100
实输出次数:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK传播延迟(tpd):0.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):1 ns
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子位置:QUAD
最小 fmax:100 MHzBase Number Matches:1

PI6C3993-5AC 数据手册

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ADVANCE INFORMATION  
PI6C3993, PI6C3994  
High-Speed Multi-Phase PLL Clock Buffer  
ProductFeatures  
ProductDescription  
• 12/100-MHz(PI6C3993),or24/185-MHz(PI6C3994)  
output operation  
The PI6C3993 and PI6C3994 High-Speed Multi-Phase PLL Clock  
Buffers offer user-selectable control over system clock functions.  
This multiple-output clock driver provides the system integrator  
withfunctionsnecessarytooptimizethetimingofhigh-performance  
computer and communication systems. Eighteen configurable out-  
puts can each drive terminated transmission lines with impedances  
as low as 50 ohms while delivering minimal and specified output  
skews at LVTTL levels. The outputs are arranged in five banks.  
Banks 1 to 4 of four outputs allow a divide function of 1 to 12, while  
simultaneouslyallowingphaseadjustmentsin625ps–1300psincre-  
ments up to 10.4ns. One of the output banks also includes an  
independent clock invert function. The feedback bank consists of  
two outputs, which allows divide-by functionality from 1 to 12 and  
limited phase adjustments. Any one of these eighteen outputs can  
be connected to the feedback input as well as driving other inputs.  
• Matched pair outputs skew <200ps  
• Zero input-to-output delay  
• 18 LVTTL 50% duty-cycle outputs capable of driving  
50-Ohmterminatedlines  
• CommercialTemp. Rangewith16outputsat185MHz  
• Industrial Temp. Range with 6 outputs at 185 MHz  
• 3.3VLVTTL/LVDifferential(LVPECL),FaultTolerant  
and Hot Insertable reference inputs  
• Phase adjustments in 625/1300ps steps up to ±10.4ns  
• Multiply/Divideratiosof(1–6,8,10,12):(1–6,8,10,12)  
• Operation up to 12x input frequency  
(inputaslowas1MHz(PI6C3993)or2MHz(PI6C3994)  
Selectable reference input is a fault tolerance feature which allows  
smooth change over to secondary clock source, when the primary  
clock source is not in operation. The reference inputs and feedback  
inputsareconfigurabletoaccommodatebothLVTTLorDifferential  
(LVPECL)inputs.ThecompletelyintegratedPLLreducesjitterand  
simplifies board layout.  
• Individual Output Bank disable for aggressive power  
management and EMI reduction  
• Output high-impedance option for testing purposes  
• FullyintegratedPLLwithLockIndicator  
• LowCycle-to-CycleJitter(<100pspeak-peak)  
• Single 3.3V ± 10% supply  
• 100-PinTQFPpackage  
PXXXX  
11/14/00  
1

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