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PI6C39912-5J PDF预览

PI6C39912-5J

更新时间: 2024-11-17 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器逻辑集成电路信息通信管理
页数 文件大小 规格书
11页 448K
描述
Eight Distributed-Output Clock Driver

PI6C39912-5J 数据手册

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PI6C39911/PI6C39912  
3.3V High Speed LVTTL or Balanced Output  
Programmable Skew Clock Buffer-SuperClock®  
Features  
Description  
• All output pair skew <100ps typical (250 Max.)  
• 12.5 MHz to 135 MHz output operation  
ThePI6C39911andPI6C39912offerselectablecontroloversystem  
clock functions. These multiple-output clock drivers provide the  
system integrator with functions necessary to optimize the timing  
of high-performance computer systems. Eight individual drivers,  
arranged as four pairs of user-controllable outputs, can each drive  
terminated transmission lines with impedances as low as 50 ohms  
whiledeliveringminimalandspecifiedoutputskewsandfull-swing  
logiclevels.  
• 3.125MHzto135MHzinputoperation  
(input as low as 3.125 MHz for 4x operation, or  
6.25 MHz for 2x operation)  
• User-selectable output functions  
— Selectable skew to 18ns  
— Inverted and non-inverted  
Each output can be hardwired to one of nine skews or function  
configurations. Delay increments of 0.7ns to 1.5ns are determined  
by the operating frequency with outputs able to skew up to ±6 time  
units from their nominal “zero” skew position. The completely  
integrated PLL allows external load and transmission line delay  
effects to be canceled. The user can create output-to-output skew  
of up to ±12 time units.  
— Operation at ½ and ¼ input frequency  
— Operation at 2X and 4X input frequency  
• Zero input-to-output delay  
• 50% duty-cycle outputs  
• LVTTLoutputsdrive50-ohmterminatedlines  
• Operates from a single 3.3V supply  
• Low operating current  
Divide-by-two and divide-by-four output functions are provided  
foradditionalflexibilityindesigningcomplexclocksystems.When  
combinedwiththeinternalPLL,thesedividefunctionsallowdistri-  
butionofalow-frequencyclockthatcanbemultipliedbytwoorfour  
attheclockdestination.This feature allows flexibility and simpli-  
fies system timing distribution design for complex high-speed  
systems.  
• 32-pinPLCCpackage  
• Jitter < 200ps peak-to-peak (< 25ps RMS)  
• AvailableinLVTTL(PI6C39911)orBalanced(PI6C39912)  
• PI6C39911isapin-to-pincompatiblewithCY7B9911V  
PinConfiguration  
LogicBlockDiagram  
Test  
Phase  
Freq.  
DET  
VCO and  
Time Unit  
Generator  
FB  
1Q0  
Filter  
1Q1  
REF  
4
3
2
1
32 31 30  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
3F1  
4F0  
4F1  
2F0  
GND  
1F1  
1F0  
6
4Q0  
4Q1  
7
4F0  
4F1  
8
V
CCQ  
32 Pin  
J
Select Inputs  
(three level)  
9
V
V
CCN  
4Q1  
CCN  
Skew  
10  
11  
12  
13  
3Q0  
3Q1  
1Q0  
1Q1  
GND  
GND  
3F0  
3F1  
4Q0  
Select  
GND  
GND  
2Q0  
2Q1  
2F0  
2F1  
14 15 16 17 18 19 20  
Matrix  
1Q0  
1Q1  
1F0  
1F1  
PS8497C  
04/10/01  
1

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