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PI6C3991-2J PDF预览

PI6C3991-2J

更新时间: 2024-09-29 22:25:35
品牌 Logo 应用领域
百利通 - PERICOM 时钟驱动器逻辑集成电路信息通信管理
页数 文件大小 规格书
11页 502K
描述
3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer SuperClock

PI6C3991-2J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFJ
包装说明:PLASTIC, LCC-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N系列:6C
输入调节:STANDARDJESD-30 代码:R-PQCC-J32
JESD-609代码:e0长度:13.97 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.035 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:0.7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:3.55 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:10
宽度:11.43 mm最小 fmax:80 MHz
Base Number Matches:1

PI6C3991-2J 数据手册

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PI6C3991  
3.3V High-Speed, Low-Voltage  
Programmable Skew Clock Buffer  
SuperClock  
Features  
Description  
• All output pair skew <100ps typical (250 Max.)  
• 3.75 MHz to 80 MHz output operation  
• User-selectable output functions  
— Selectable skew to 18ns  
PI6C3991 offers selectable control over system clock functions.  
These multiple-output clock drivers provide the system integrator  
with functions necessary to optimize the timing of high-perfor-  
mancecomputersystems.Eightindividualdrivers,arrangedasfour  
pairs of user-controllable outputs, can each drive terminated trans-  
mission lines with impedances as low as 50 ohms while delivering  
minimal and specified output skews and full-swing logic levels  
(LVTTL).  
— Inverted and Non-Inverted  
— Operation at ½ and ¼ input frequency  
— Operation at 2X and 4X input frequency  
(input as low as 3.75 MHz, x4 operation)  
Each output can be hardwired to one of nine skews or function  
configurations. Delay increments of 0.7ns to 1.5ns are determined  
by the operating frequency with outputs able to skew up to ±6 time  
units from their nominal “zero” skew position. The completely  
integrated PLL allows external load and transmission line delay  
effects to be canceled. The user can create output-to-output skew  
up to ±12 time units.  
• Zero input-to-output delay  
• 50% duty-cycle outputs  
• LVTTLoutputsdrive50-ohmterminatedlines  
• Operates from a single 3.3V supply  
• Low operating current  
Divide-by-two and divide-by-four output functions are provided  
foradditionalflexibilityindesigningcomplexclocksystems.When  
combined with the internal PLL, these divide functions allow  
distribution of a low-frequency clock that can be multiplied by  
two or four at the clock destination. This feature allows flexibility  
and simplifies system timing distribution design for complex  
high-speed systems.  
• Availablein32-pinPLCC(J)package  
• Jitter < 200ps peak-to-peak (< 25ps RMS)  
PinConfiguration  
LogicBlockDiagram  
Test  
Phase  
Freq.  
DET  
FB  
VCO and  
Time Unit  
Generator  
Filter  
REF  
4
3
2
1
32 31 30  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
3F1  
4F0  
4F1  
2F0  
GND  
1F1  
1F0  
FS  
6
4Q0  
4Q1  
7
4F0  
4F1  
8
V
CCQ  
32-Pin  
J
Select Inputs  
(three level)  
9
V
V
CCN  
4Q1  
CCN  
Skew  
3Q0  
3Q1  
10  
11  
12  
13  
1Q0  
1Q1  
GND  
GND  
3F0  
3F1  
4Q0  
Select  
GND  
GND  
2Q0  
2Q1  
2F0  
2F1  
Matrix  
14 15 16 17 18 19 20  
1Q0  
1Q1  
1F0  
1F1  
PS8450B  
04/09/01  
1

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