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PI6C3991-5JI

更新时间: 2024-09-29 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器
页数 文件大小 规格书
12页 449K
描述
Eight Distributed-Output Clock Driver

PI6C3991-5JI 数据手册

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PI6C3991  
3.3V High Speed Low-Voltage  
Programmable Skew Clock Buffer  
SuperClockTM  
Features  
Description  
• All output pair skew <100ps typical (250 Max.)  
• 3.75 MHz to 80 MHz output operation  
• User-selectable output functions  
— Selectable skew to 18ns  
ThePI6C3991offersselectablecontroloversystemclockfunctions.  
These multiple-output clock drivers provide the system integrator  
withfunctionsnecessarytooptimizethetimingofhigh-performance  
computer systems. Eight individual drivers, arranged as four pairs  
ofuser-controllableoutputs,caneachdriveterminatedtransmission  
lineswithimpedancesaslowas50Ohmwhiledeliveringminimaland  
specified output skews and full-swing logic levels (LVTTL).  
— Inverted and Non-Inverted  
— Operation at ½ and ¼ input frequency  
Each output can be hardwired to one of nine delay or function  
configurations.Delayincrementsof0.7nsto1.5nsaredeterminedby  
theoperatingfrequencywithoutputsabletoskewupto±6timeunits  
fromtheirnominal“zero”skewposition.Thecompletelyintegrated  
PLL allows external load and transmission line delay effects to be  
canceled. The user can create output-to-output delays of up to ±12  
time units.  
— Operation at 2X and 4X input frequency  
(input as low as 3.75 MHz)  
• Zero input-to-output delay  
• 50% duty-cycle outputs  
• LVTTL outputs drive 50 Ohm terminated lines  
• Operates from a single 3.3V supply  
• Low operating current  
Divide-by-twoanddivide-by-fouroutputfunctionsareprovidedfor  
additional flexibility in designing complex clock systems. When  
combinedwiththeinternalPLL,thesedividefunctionsallowdistri-  
butionofalow-frequencyclockthatcanbemultipliedbytwoorfour  
at the clock destination. This facility minimizes clock distribution  
difficulty while allowing maximum system user-clock speed and  
flexibility.  
• Availablein32-pinPLCC(J)package  
• Jitter < 200ps peak-to-peak (< 25ps RMS)  
LogicBlockDiagram  
PinConfiguration  
Test  
Phase  
Freq.  
DET  
FB  
VCO and  
Time Unit  
Generator  
Filter  
REF  
4
3
2
1
32 31 30  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
3F1  
4F0  
4F1  
2F0  
GND  
1F1  
1F0  
FS  
6
7
4Q0  
4Q1  
4F0  
4F1  
8
V
CCQ  
32-Pin  
J
Select Inputs  
(three level)  
9
V
V
CCN  
4Q1  
CCN  
Skew  
3Q0  
3Q1  
10  
11  
12  
13  
1Q0  
1Q1  
GND  
GND  
3F0  
3F1  
4Q0  
Select  
GND  
GND  
2Q0  
2Q1  
2F0  
2F1  
Matrix  
14 15 16 17 18 19 20  
1Q0  
1Q1  
1F0  
1F1  
PS8450  
01/27/00  
1

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PI6C3991AJ PERICOM

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