PI6C2501
Phase-Locked Loop Clock Driver
ProductFeatures
Product Description
The PI6C2501 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the CLK_OUT output to the
feedback FB_IN input, the propagation delay from the CLK_IN
input to CLK_OUT output will be nearly zero.
• High-Performance,Phase-Locked-LoopClockDistribution
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Zero Input-to-Output delay
• Lowjitter:Cycle-to-Cyclejitter±100psmax.
Application
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers, such as the
PI6C2509Q, or PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends using a zero-delay buffer and
an eighteen output non-zero-delay buffer. As shown in Figure 1,
this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
• Operatesat3.3VVCC
• Wide range of Clock Frequencies up to 80 MHz
• Package:Plastic8-pinSOIC(W)
ProductPinConfiguration
LogicBlockDiagram
8
7
6
5
AGND
GND
1
2
3
4
CLK_IN
CLK_IN
CLK_OUT
8-Pin
W
AV
CC
PLL
FB_IN
AVCC
CLK_OUT
GND
V
FB_IN
CC
Feedback
Zero Delay
Buffer
PI6C2501
18 Outputs
Non-PLL
Buffer
C
CLK_OUT
17
Reference
Clock
Signal
Figure 1. This Combination Provides Zero-Delay Between
the Reference Clock Signal and 17 Outputs
PS8381A
07/17/00
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