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PDM4M3120S12M PDF预览

PDM4M3120S12M

更新时间: 2024-02-15 22:24:04
品牌 Logo 应用领域
IXYS 静态存储器内存集成电路
页数 文件大小 规格书
10页 108K
描述
SRAM Module, 1MX32, 12ns, CMOS, SIMM-72

PDM4M3120S12M 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SIMM
包装说明:SIMM-72针数:72
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:12 nsJESD-30 代码:R-XSMA-N72
内存密度:33554432 bit内存集成电路类型:SRAM MODULE
内存宽度:32功能数量:1
端子数量:72字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX32封装主体材料:UNSPECIFIED
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:SINGLE处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

PDM4M3120S12M 数据手册

 浏览型号PDM4M3120S12M的Datasheet PDF文件第3页浏览型号PDM4M3120S12M的Datasheet PDF文件第4页浏览型号PDM4M3120S12M的Datasheet PDF文件第5页浏览型号PDM4M3120S12M的Datasheet PDF文件第7页浏览型号PDM4M3120S12M的Datasheet PDF文件第8页浏览型号PDM4M3120S12M的Datasheet PDF文件第9页 
PRELIMINARY  
PDM4M3120  
AC Electrical Characteristics (Vcc = 3.3V ± 10%, T = 0°C to +70°C)  
A
PDM4M3120SXXZ, PDM4M3120SXXM  
-20 ns -15 ns -12 ns  
Min. Max. Min. Max. Min. Max.  
Symbol  
Parameter  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
20  
15  
12  
ns  
ns  
RC  
Address Access Time  
20  
15  
12  
AA  
Chip Select Access Time  
3
20  
10  
7
3
15  
8
3
12  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACS  
(1)  
Chip Select to Output inLow-Z  
Output Enable to Output Valid  
Output Enable to Output in Low-Z  
Chip Deselect to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
Chip Select to Power-Up Time  
Chip Deselect to Power-Down Time  
CLZ  
OE  
0
0
0
(1)  
(1)  
7
7
OLZ  
3
3
3
CHZ  
OHZ  
OH  
(1)  
7
7
7
20  
15  
12  
(1)  
0
0
0
PU  
(1)  
PD  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
20  
12  
12  
0
15  
10  
10  
0
7
12  
10  
10  
0
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CW  
AW  
AS  
Chip Select to End of Write  
Address Valid to End of Write  
Address Setup Time  
Write Pulse Width  
15  
3
7
13  
3
12  
3
WP  
WR  
WHZ  
DW  
DH  
Write Recovery Time  
(1)  
Write Enable to Output in High-Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
12  
0
10  
0
10  
0
(1)  
OW  
0
0
0
NOTE 1. This parameter is determined by device characteristics but is not production tested.  
6
Rev 1.1  

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