5秒后页面跳转
PDM4M3120S15M PDF预览

PDM4M3120S15M

更新时间: 2024-02-11 10:25:58
品牌 Logo 应用领域
IXYS 静态存储器
页数 文件大小 规格书
10页 108K
描述
SRAM Module, 1MX32, 15ns, CMOS, SIMM-72

PDM4M3120S15M 数据手册

 浏览型号PDM4M3120S15M的Datasheet PDF文件第2页浏览型号PDM4M3120S15M的Datasheet PDF文件第3页浏览型号PDM4M3120S15M的Datasheet PDF文件第4页浏览型号PDM4M3120S15M的Datasheet PDF文件第5页浏览型号PDM4M3120S15M的Datasheet PDF文件第6页浏览型号PDM4M3120S15M的Datasheet PDF文件第7页 
PRELIMINARY  
PDM4M3120  
3.3V, 1M x 32 CMOS  
Static RAM Module  
1
The PDM4M3120 is packaged in a 72-pin FR-4 ZIP  
(Zig-zag In-line vertical Package) or a 72-pin SIMM or  
Angled SIMM (Single In-line Memory Module). The  
Features  
High-density 3.3V, 4 megabyte Static RAM  
module  
Low profile 72-pin ZIP (Zig-zag In-line vertical  
Package) or 72-pin SIMM or Angled SIMM  
(Single In-line Memory Module)  
Fast access time: 12 ns (max.)  
Surface mounted plastic components on an  
epoxy laminate (FR-4) substrate.  
Single 3.3V (±10%) power supply  
Multiple V pins and decoupling capacitors for  
maximum noise immunity  
Inputs/ outputs directly TTL compatible  
ZIP configuration allows 72 pins to be placed on a 2  
package 3.950" long and 0.365" wide. At only 0.590"  
high, this low-profile package is ideal for systems  
with minimum board spacing. The SIMM configura-  
tion allows use of edge mounted sockets to secure the 3  
module.  
All inputs and outputs of the PDM4M3120 are TTL  
compatible and operate from a single 3.3V supply.  
Full asynchronous circuitry requires no clock or  
refresh for operation and provides equal access and  
cycle times for ease of use.  
SS  
4
Four identification pins (PD0, PD1, PD2, PD3) are pro-  
vided for applications in which different density  
versions of the module are used. In this way, the tar-  
5
Description  
The PDM4M3120 is a 3.3V, 1M x 32 static RAM  
module constructed on an epoxy laminate (FR-4)  
substrate using eight 1M x 4 static RAMs in plastic  
SOJ packages. Availability of four chip select lines  
(one for each of four RAMs) provides byte access.  
The PDM4M3120 is available with access times as  
fast as 12 ns with minimal power consumption.  
get system can read the respective levels of PD0, PD1, 6  
PD2, PD3 to determine a 1M depth.  
7
9
Functional Block Diagram  
CS1  
CS2  
CS3  
CS4  
20  
ADDRESS  
WE  
4
10  
11  
12  
PD3-PD0  
1M x 32  
RAM  
OE  
8
8
8
8
I/O31-I/O0  
Rev 1.1  
1

与PDM4M3120S15M相关器件

型号 品牌 描述 获取价格 数据表
PDM4M3120S15Z IXYS SRAM Module, 1MX32, 15ns, CMOS, ZIP-72

获取价格

PDM4M3120S20AM IXYS SRAM Module, 1MX32, 20ns, CMOS, ANGLED, SIMM-72

获取价格

PDM4M3120S20M IXYS SRAM Module, 1MX32, 20ns, CMOS, SIMM-72

获取价格

PDM4M4030S25AM IXYS SRAM

获取价格

PDM4M4050S10AM IXYS SRAM

获取价格

PDM4M4050S15M IXYS SRAM

获取价格