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PCA9541APW/01 PDF预览

PCA9541APW/01

更新时间： 2024-09-17 05:59:47
品牌 Logo 应用领域
恩智浦 - NXP 调节器微控制器和处理器外围集成电路uCs集成电路uPs集成电路光电二极管
页数 文件大小 规格书
41页 211K
描述
2-to-1 I2C-bus master selector with interrupt logic and reset

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PCA9541APW/01 技术参数

生命周期：Active零件包装代码：TSSOP
包装说明：4.40 MM WIDTH, PLASTIC, MO-153, SOT403-1, TSSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.55JESD-30 代码：R-PDSO-G16
长度：5 mm端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3.6 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

PCA9541APW/01 数据手册

 浏览型号PCA9541APW/01的Datasheet PDF文件第2页浏览型号PCA9541APW/01的Datasheet PDF文件第3页浏览型号PCA9541APW/01的Datasheet PDF文件第4页浏览型号PCA9541APW/01的Datasheet PDF文件第5页浏览型号PCA9541APW/01的Datasheet PDF文件第6页浏览型号PCA9541APW/01的Datasheet PDF文件第7页 
PCA9541A  
2-to-1 I2C-bus master selector with interrupt logic and reset  
Rev. 03 — 16 July 2009  
Product data sheet  
1. General description  
The PCA9541A is a 2-to-1 I2C-bus master selector designed for high reliability dual  
master I2C-bus applications where system operation is required, even when one master  
fails or the controller card is removed for maintenance. The two masters (for example,  
primary and back-up) are located on separate I2C-buses that connect to the same  
downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master  
and are used to select one master at a time. Either master at any time can gain control of  
the slave devices if the other master is disabled or removed from the system. The failed  
master is isolated from the system and will not affect communication between the on-line  
master and the slave devices on the downstream I2C-bus.  
Two versions are offered for different architectures. PCA9541A/01 with channel 0 selected  
at start-up, and PCA9541A/03 with no channel selected after start-up.  
The interrupt outputs are used to provide an indication of which master has control of the  
bus. One interrupt input (INT_IN) collects downstream information and propagates it to  
the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let  
the previous bus master know that it is not in control of the bus anymore and to indicate  
the completion of the bus recovery/initialization sequence. Those interrupts can be  
disabled and will not generate an interrupt if the masking option is set.  
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a  
STOP condition in order to set the downstream I2C-bus devices to an initialized state  
before actually switching the channel to the selected master.  
An interrupt is sent to the upstream channel when the recovery/initialization procedure is  
completed.  
An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt  
if a channel switch occurs during a non-idle bus condition. This function is enabled when  
the PCA9541A recovery/initialization is not used. The interrupt signal informs the master  
that an external I2C-bus recovery/initialization needs to be performed. It can be disabled  
and an interrupt will not be generated.  
The pass gates of the switches are constructed such that the VDD pin can be used to limit  
the maximum high voltage, which will be passed by the PCA9541A. This allows the use of  
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate  
with 5 V devices without any additional protection.  
The PCA9541A does not isolate the capacitive loading on either side of the device, so the  
designer must take into account all trace and device capacitances on both sides of the  
device, and pull-up resistors must be used on all channels.  
External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O  
pins are 6.0 V tolerant.  
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PCA9541APW/01 替代型号

型号 品牌 替代类型 描述 数据表
PCA9541APW/03 NXP

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