Datasheet > PCA9541PW/02

PCA9541PW/02

更新时间： 2024-09-17 03:40:39

品牌	Logo	应用领域
恩智浦 - NXP		调节器
页数	文件大小	规格书
43页	217K
描述
2-to-1 I2C-bus master selector with interrupt logic and reset

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PCA9541PW/02 数据手册

PCA9541

2-to-1 I²C-bus master selector with interrupt logic and reset

Rev. 05 — 1 October 2007

Product data sheet

1. General description

The PCA9541 is a 2-to-1 I²C-bus master selector designed for high reliability dual master

I²C-bus applications where system operation is required, even when one master fails or

the controller card is removed for maintenance. The two masters (for example, primary

and back-up) are located on separate I²C-buses that connect to the same downstream

I²C-bus slave devices. I²C-bus commands are sent by either I²C-bus master and are used

to select one master at a time. Either master at any time can gain control of the slave

devices if the other master is disabled or removed from the system. The failed master is

isolated from the system and will not affect communication between the on-line master

and the slave devices on the downstream I²C-bus.

Three versions are offered for different architectures. PCA9541/01 with channel 0

selected at start-up, PCA9541/02 with channel 0 selected after start-up and after STOP

condition is detected, and PCA9541/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the

bus. One interrupt input (INT_IN) collects downstream information and propagates it to

the 2 upstream I²C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let

the previous bus master know that it is not in control of the bus anymore and to indicate

the completion of the bus recovery/initialization sequence. Those interrupts can be

disabled and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I²C-bus devices to an initialized state

before actually switching the channel to the selected master.

An interrupt is sent to the upstream channel when the recovery/initialization procedure is

completed.

An internal bus sensor senses the downstream I²C-bus trafﬁc and generates an interrupt

if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541 recovery/initialization is not used. The interrupt signal informs the master

that an external I²C-bus recovery/initialization needs to be performed. It can be disabled

and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V_DDpin can be used to limit

the maximum high voltage, which will be passed by the PCA9541. This allows the use of

different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate

with 5 V devices without any additional protection.

The PCA9541 does not isolate the capacitive loading on either side of the device, so the

designer must take into account all trace and device capacitances on both sides of the

device, and pull-up resistors must be used on all channels.

12 3 4 5 6 7...43

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与PCA9541PW/02相关器件

型号	品牌	获取价格	描述	数据表
PCA9541PW/03	NXP	获取价格	2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541PW/03-T	NXP	获取价格	2-to-1 I²C-bus master selector with interrupt logic and reset
PCA9542	NXP	获取价格	2-channel I2C multiplexer and interrupt controller
PCA9542A	NXP	获取价格	2-channel I2C-bus multiplexer and interrupt logic
PCA9542AD	NXP	获取价格	2-channel I2C-bus multiplexer and interrupt logic
PCA9542AD,112	NXP	获取价格	PCA9542A - 2-channel I2C-bus multiplexer and interrupt logic SOIC 14-Pin
PCA9542APW	NXP	获取价格	2-channel I2C-bus multiplexer and interrupt logic
PCA9542APW,118	NXP	获取价格	PCA9542A - 2-channel I2C-bus multiplexer and interrupt logic TSSOP 14-Pin
PCA9542APW/DG,118	NXP	获取价格	PCA9542A - 2-channel I2C-bus multiplexer and interrupt logic TSSOP 14-Pin
PCA9542APW-T	NXP	获取价格	2-channel I2C multiplexer and interrupt logic - # of Addresses: 8 ; I2C-bus: 400 kHz; Inpu

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