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PCA9541D/01

更新时间： 2024-11-07 02:54:15
品牌 Logo 应用领域
恩智浦 - NXP 调节器
页数 文件大小 规格书
43页 217K
描述
2-to-1 I2C-bus master selector with interrupt logic and reset

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PCA9541D/01 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.59JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
湿度敏感等级：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Bus Controllers
最大压摆率：0.6 mA最大供电电压：5.5 V
最小供电电压：2.3 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：3.9 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

PCA9541D/01 数据手册

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PCA9541  
2-to-1 I2C-bus master selector with interrupt logic and reset  
Rev. 05 — 1 October 2007  
Product data sheet  
1. General description  
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual master  
I2C-bus applications where system operation is required, even when one master fails or  
the controller card is removed for maintenance. The two masters (for example, primary  
and back-up) are located on separate I2C-buses that connect to the same downstream  
I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are used  
to select one master at a time. Either master at any time can gain control of the slave  
devices if the other master is disabled or removed from the system. The failed master is  
isolated from the system and will not affect communication between the on-line master  
and the slave devices on the downstream I2C-bus.  
Three versions are offered for different architectures. PCA9541/01 with channel 0  
selected at start-up, PCA9541/02 with channel 0 selected after start-up and after STOP  
condition is detected, and PCA9541/03 with no channel selected after start-up.  
The interrupt outputs are used to provide an indication of which master has control of the  
bus. One interrupt input (INT_IN) collects downstream information and propagates it to  
the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let  
the previous bus master know that it is not in control of the bus anymore and to indicate  
the completion of the bus recovery/initialization sequence. Those interrupts can be  
disabled and will not generate an interrupt if the masking option is set.  
A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a  
STOP condition in order to set the downstream I2C-bus devices to an initialized state  
before actually switching the channel to the selected master.  
An interrupt is sent to the upstream channel when the recovery/initialization procedure is  
completed.  
An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt  
if a channel switch occurs during a non-idle bus condition. This function is enabled when  
the PCA9541 recovery/initialization is not used. The interrupt signal informs the master  
that an external I2C-bus recovery/initialization needs to be performed. It can be disabled  
and an interrupt will not be generated.  
The pass gates of the switches are constructed such that the VDD pin can be used to limit  
the maximum high voltage, which will be passed by the PCA9541. This allows the use of  
different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate  
with 5 V devices without any additional protection.  
The PCA9541 does not isolate the capacitive loading on either side of the device, so the  
designer must take into account all trace and device capacitances on both sides of the  
device, and pull-up resistors must be used on all channels.  
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