Datasheet > P620-30DC

P620-30DC

更新时间： 2024-09-12 03:43:43

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
6页	206K
描述
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

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P620-30DC 数据手册

PLL620-30

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

DIE CONFIGURATION

FEATURES

65 mil

•

65MHz to 130MHz Crystal input.

Output range: 32.5MHz – 130MHz (no PLL).

Low Injection Power for crystal, 50uW.

Complementary outputs: PECL or LVDS.

Selectable OE Logic

Supports 2.5V or 3.3V-Power Supply.

Available in die form.

(1550,1475)

24 23 22 21

GNDBUF

XIN

N/C

Die ID:

A2020-20A

LVDSB

PECLB

XOUT

N/C

Thickness 10 mil.

VDDBUF

DESCRIPTION

S2^

VDDBUF

PECL

The PLL620-30 is a XO IC specifically designed to

drive fundamental or 3^rdOT crystals from 65MHz to

130MHz, with selectable PECL or LVDS outputs and

OE logic (enable high or enable low). Its design was

optimized to tolerate higher limits of interelectrode

capacitance and bonding capacitance to improve

yield. It achieves very low current into the crystal

resulting in better overall stability.

CTRL

LVDS

C502A

N/C

OUTSEL^

(0,0)

DIE SPECIFICATIONS

OUTPUT SELECTION AND ENABLE

OUTSEL

Name

Value

Selected Output

(Pad #9)

Size

62 x 65 mil

GND

LVDS

Reverse side

Pad dimensions

Thickness

PECL (default)

80 micron x 80 micron

10 mil

OESEL

OE_CTRL

State

(Pad #25) (Pad #30)

Tri-state

Output enabled (default)

Tri-state

BLOCK DIAGRAM

1 (default)

Pad #9, #25: Bond to GND to set to “0”. Internal pull up.

Pad #30: Logical states defined by PECL levels if OESEL is “1”

Logical states defined by CMOS levels if OESEL is “0”

Oscillator

Amplifier

OUTPUT FREQUENCY SELECTOR

XIN

Output

XOUT

PLL620-30

Input/2

Input

1(Default)*

*Internally set to ‘Default’ through 60KΩ pull-up resistor

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1

12 3 4 5 6

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