Datasheet > P620-89OC

P620-89OC

更新时间： 2024-09-12 09:55:55

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
6页	197K
描述
Low Phase Noise XO (9.5-65MHz Output)

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数据手册

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P620-89OC 数据手册

PLL620-88/-89

Low Phase Noise XO (9.5-65MHz Output)

FEATURES

PIN CONFIGURATION

•

19MHz to 65MHz crystal input.

Output range: 9.5MHz – 65MHz

Complementary outputs: PECL or LVDS output.

Selectable OE Logic (enable high or enable low).

Supports 2.5V or 3.3V Power Supply.

Available in 16 pin TSSOP package.

VDD

XIN

DNC

XOUT

DNC

GNDBUF

QBAR

VDDBUF

DESCRIPTION

N/C

GNDBUF

GND

The PLL620-88 (PECL) and PLL620-89 (LVDS) are

XO ICs specifically designed to work with

GND

fundamental or 3^rdOT crystals between 19MHz and

65MHz. The selectable divide by two feature extends

the operation range from 9.5MHz to 65MHz. They

require very low current into the crystal resulting in

better overall stability. The OE logic feature allows

selection of enable high or enable low.

OUTPUT SELECTION AND ENABLE

OE_SELECT

OE_CTRL

State

Tri-state

1 (Default) Output enabled

0 (Default) Output enabled

BLOCK DIAGRAM

1 (Default)

Tri-state

Input selection: Bond to GND to set to “0”, bond to VDD to set to “1”

No connection results to “default” setting through

internal pull-up/-down.

OE_CTRL:

Logical states defined by PECL levels if

OE_SELECT is “1”

Logical states defined by CMOS levels if

OE_SELECT is “0”

Oscillator

Amplifier

X+

X-

OUTPUT FREQUENCY DIVIDE BY

TWO SELECTOR

PLL620-8X Block Diagram

Output

Intput/2

Input

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 1

12 3 4 5 6

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