Datasheet > P620-3XSC

P620-3XSC

更新时间： 2024-09-12 09:55:55

品牌	Logo	应用领域
PLL		石英晶振
页数	文件大小	规格书
6页	216K
描述
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

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数据手册

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P620-3XSC 数据手册

PLL620-38/39

PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

FEATURES

PIN CONFIGURATION

•

65MHz to 130MHz Crystal input.

Output range: 32.5MHz – 130MHz (no PLL).

Low Injection Power for crystal, 50uW.

PECL (PLL620-38) or LVDS output (PLL620-39).

Supports 2.5V or 3.3V-Power Supply.

Available in 16-Pin TSSOP.

V D D

XIN

D N C

XOU T

D N C

G N D

CLK C

V D D

DESCRIPTION

S2^

OE _CT RL

D N C

CLK T

G N D B U F

G N D

The PLL620-38/-39 is a family of XO IC’s specifically

designed to work with high frequency fundamental or

3^rdOT crystals from 65MHz to 130MHz, with

selectable PECL or LVDS outputs. They achieve

very low current into the crystal resulting in better

overall stability. Their very low jitter makes them

ideal for the most demanding timing requirements.

G N D

Note: ^ designates internal pull-up resistor.

BLOCK DIAGRAM

OUTPUT ENABLE LOGICAL LEVELS

Part #

(Default)

State

Output enabled

PLL620-38

Oscillator

Tri-state

Amplifier

XIN

PLL620-39

Output enabled

(Default)

XOUT

PLL620-38/-39

OE input: Logical states defined by PECL levels for PLL620-38

Logical states defined by CMOS levels for PLL620-39

OUTPUT FREQUENCY SELECTOR

Output

Input/2

Input

1(Default)*

*Internally set to ‘Default’ through 60KΩ pull-up resistor

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 1

12 3 4 5 6

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