PLL620-80
Low Phase Noise XO (9.5-65MHz Output)
DIE CONFIGURATION
FEATURES
65 mil
•
•
•
•
19MHz to 65MHz crystal input.
Output range: 9.5MHz – 65MHz
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 2.5V or 3.3V Power Supply.
Available in die form.
(1550,1475)
25
24 23
22 21
20
19
18
17
16
GNDBUF
CMOS
26
XIN
Die ID:
A2020-20B
•
•
15
14
LVDSB
PECLB
27
28
XOUT
N/C
13
12
VDDBUF
VDDBUF
DESCRIPTION
S2^
29
The PLL620-80 is a XO IC specifically designed to
work with fundamental or 3rd OT crystals between
19MHz and 65MHz. The selectable divide by two
feature extends the operation range from 9.5MHz to
65MHz. It requires very low current into the crystal
resulting in better overall stability. The OE logic
feature allows selection of enable high or enable low.
Furthermore, it provides selectable CMOS, PECL or
LVDS outputs.
11
PECL
OE
CTRL
30
31
10
9
LVDS
C502A
N/C
OE_SEL^
2
3
4
5
6
7
8
1
(0,0)
Y
X
OUTPUT SELECTION AND ENABLE
OUT_SEL1* OUT_SEL0*
Selected Output*
(Pad 18)
(Pad 25)
DIE SPECIFICATIONS
0
0
1
1
0
1
0
1
High Drive CMOS
Standard CMOS
LVDS
Name
Value
Size
62 x 65 mil
GND
Reverse side
Pad dimensions
Thickness
PECL (default)
80 micron x 80 micron
10 mil
OE_SELECT
(Pad 9)
OE_CTRL
(Pad 30)
State
0
Tri-state
0
1 (Default) Output enabled
0 (Default) Output enabled
BLOCK DIAGRAM
1 (Default)
1
Tri-state
OE
Q
Pads #9, #18 & #25: Bond to GND to set to “0”,
No connection results to “default” setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1”
Logical states defined by CMOS levels if OE_SELECT is “0”
Q
Oscillator
Amplifier
XIN
OUTPUT FREQUENCY SELECTOR
S2
XOUT
S2
Output
PLL620-80
0
Input/2
Input
1(Default)*
*Internally set to ‘Default’ through 60KΩ pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1