Datasheet > 晶体管 > 小信号双极晶体管> NSVDTA114YM3T5G

NSVDTA114YM3T5G

更新时间： 2024-11-30 11:01:35

品牌	Logo	应用领域
安森美 - ONSEMI		小信号双极晶体管数字晶体管
页数	文件大小	规格书
13页	108K
描述
PNP 双极数字晶体管 (BRT)

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NSVDTA114YM3T5G 数据手册

DTA114EET1 Series

Preferred Devices

Bias Resistor Transistors

PNP Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The Bias Resistor

Transistor (BRT) contains a single transistor with a monolithic bias

network consisting of two resistors; a series base resistor and a

base−emitter resistor. The BRT eliminates these individual

components by integrating them into a single device. The use of a BRT

can reduce both system cost and board space. The device is housed in

the SC−75/SOT−416 package which is designed for low power

surface mount applications.

http://onsemi.com

PNP SILICON BIAS

RESISTOR TRANSISTORS

PIN 3

COLLECTOR

(OUTPUT)

PIN 1

Features

BASE

(INPUT)

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

PIN 2

EMITTER

(GROUND)

• The SC−75/SOT−416 package can be soldered using wave or reflow.

The modified gull−winged leads absorb thermal stress during

soldering eliminating the possibility of damage to the die.

• Pb−Free Packages are Available

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Collector-Base Voltage

Symbol

Value

Unit

Vdc

SC−75 (SOT−416)

CASE 463

CBO

CEO

STYLE 1

Collector-Emitter Voltage

Collector Current

Vdc

100

mAdc

MARKING DIAGRAM

THERMAL CHARACTERISTICS

Rating

Symbol

Value

Unit

Total Device Dissipation, FR−4 Board

(Note 1) @ T = 25°C

Derate above 25°C

200

1.6

mW/°C

xx M G

Thermal Resistance, Junction−to−Ambient

(Note 1)

600

°C/W

Total Device Dissipation, FR−4 Board

Specific Device Code

xx = (Refer to page 2)

Date Code*

(Note 2) @ T = 25°C

Derate above 25°C

300

2.4

mW/°C

Thermal Resistance, Junction−to−Ambient

(Note 2)

400

°C/W

Pb−Free Package

(Note: Microdot may be in either location)

Junction and Storage Temperature Range

T , T

−55 to

+150

°C

*Date Code orientation may vary depending

upon manufacturing location.

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. FR−4 @ Minimum Pad.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

2. FR−4 @ 1.0 × 1.0 Inch Pad.

Preferred devices are recommended choices for future use

and best overall value.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

March, 2006 − Rev. 6

DTA114EET1/D

12 3 4 5 6 7...13

中文翻译

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与NSVDTA114YM3T5G相关器件

型号	品牌	获取价格	描述	数据表
NSVDTA115EET1G	ONSEMI	获取价格	PNP 双极数字晶体管 (BRT)
NSVDTA123EM3T5G	ONSEMI	获取价格	PNP Bipolar Digital Transistor (BRT)
NSVDTA123JM3T5G	ONSEMI	获取价格	PNP Bipolar Digital Transistor (BRT)
NSVDTA143EM3T5G	ONSEMI	获取价格	PNP Bipolar Digital Transistor (BRT)
NSVDTA143ZET1G	ONSEMI	获取价格	PNP 双极数字晶体管 (BRT)
NSVDTA144EET1G	ONSEMI	获取价格	PNP 双极数字晶体管 (BRT)
NSVDTA144WET1G	ONSEMI	获取价格	PNP 双极数字晶体管 (BRT)
NSVDTC113EM3T5G	ONSEMI	获取价格	NPN Bipolar Digital Transistor (BRT)
NSVDTC114YM3T5G	ONSEMI	获取价格	NPN 双极数字晶体管 (BRT)
NSVDTC123EM3T5G	ONSEMI	获取价格	NPN Bipolar Digital Transistor (BRT)

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