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NSVDTA123EM3T5G

更新时间： 2024-11-30 11:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管晶体管
页数 文件大小 规格书
13页 108K
描述
PNP Bipolar Digital Transistor (BRT)

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中文翻译

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NSVDTA123EM3T5G 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：SMALL OUTLINE, R-PDSO-F3Reach Compliance Code：compliant
ECCN代码：EAR99Factory Lead Time：8 weeks
风险等级：5.78其他特性：BUILT IN BIAS RESISTANCE RATIO IS 1
最大集电极电流 (IC)：0.1 A集电极-发射极最大电压：50 V
配置：SINGLE WITH BUILT-IN RESISTOR最小直流电流增益 (hFE)：8
JESD-30 代码：R-PDSO-F3JESD-609代码：e3
湿度敏感等级：1元件数量：1
端子数量：3封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260极性/信道类型：PNP
参考标准：AEC-Q101表面贴装：YES
端子面层：Tin (Sn)端子形式：FLAT
端子位置：DUAL处于峰值回流温度下的最长时间：30
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

NSVDTA123EM3T5G 数据手册

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DTA114EET1 Series  
Preferred Devices  
Bias Resistor Transistors  
PNP Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The Bias Resistor  
Transistor (BRT) contains a single transistor with a monolithic bias  
network consisting of two resistors; a series base resistor and a  
base−emitter resistor. The BRT eliminates these individual  
components by integrating them into a single device. The use of a BRT  
can reduce both system cost and board space. The device is housed in  
the SC−75/SOT−416 package which is designed for low power  
surface mount applications.  
http://onsemi.com  
PNP SILICON BIAS  
RESISTOR TRANSISTORS  
PIN 3  
COLLECTOR  
(OUTPUT)  
PIN 1  
R1  
Features  
BASE  
(INPUT)  
R2  
• Simplifies Circuit Design  
• Reduces Board Space  
• Reduces Component Count  
PIN 2  
EMITTER  
(GROUND)  
• The SC−75/SOT−416 package can be soldered using wave or reflow.  
The modified gull−winged leads absorb thermal stress during  
soldering eliminating the possibility of damage to the die.  
• Pb−Free Packages are Available  
3
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
Rating  
Collector-Base Voltage  
Symbol  
Value  
50  
Unit  
Vdc  
SC−75 (SOT−416)  
CASE 463  
V
V
CBO  
CEO  
STYLE 1  
Collector-Emitter Voltage  
Collector Current  
50  
Vdc  
I
100  
mAdc  
C
MARKING DIAGRAM  
THERMAL CHARACTERISTICS  
Rating  
Symbol  
Value  
Unit  
Total Device Dissipation, FR−4 Board  
P
D
(Note 1) @ T = 25°C  
Derate above 25°C  
200  
1.6  
mW  
mW/°C  
A
xx M G  
G
Thermal Resistance, Junction−to−Ambient  
(Note 1)  
R
q
JA  
600  
°C/W  
Total Device Dissipation, FR−4 Board  
P
D
xx  
=
Specific Device Code  
xx = (Refer to page 2)  
Date Code*  
(Note 2) @ T = 25°C  
Derate above 25°C  
300  
2.4  
mW  
mW/°C  
A
M
G
=
=
Thermal Resistance, Junction−to−Ambient  
(Note 2)  
R
q
JA  
400  
°C/W  
Pb−Free Package  
(Note: Microdot may be in either location)  
Junction and Storage Temperature Range  
T , T  
−55 to  
+150  
°C  
*Date Code orientation may vary depending  
upon manufacturing location.  
J
stg  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. FR−4 @ Minimum Pad.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
2. FR−4 @ 1.0 × 1.0 Inch Pad.  
Preferred devices are recommended choices for future use  
and best overall value.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 6  
DTA114EET1/D  
 
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