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NL37WZ14 PDF预览

NL37WZ14

更新时间: 2024-11-11 22:13:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
6页 68K
描述
Triple Schmitt-Trigger Inverter

NL37WZ14 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.73逻辑集成电路类型:INVERTER
Base Number Matches:1

NL37WZ14 数据手册

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NL37WZ14  
Triple Schmitt−Trigger  
Inverter  
The NL37WZ14 is a high performance triple inverter with  
Schmitt−Trigger inputs operating from a 1.65 to 5.5 V supply.  
Pin configuration and function are the same as the NL37WZ04, but  
the inputs have hysteresis, and with its Schmitt trigger function, the  
NL37WZ14 can be used as a line receiver which will receive slow  
input signals. The NL37WZ14 is capable of transforming slowly  
changing input signals into sharply defined, jitter−free output signals.  
In addition, it has a greater noise margin than conventional inverters.  
The NL37WZ14 has hysteresis between the positive−going and the  
negative−going input thresholds (typically 1.0 V) which is determined  
internally by transistor ratios and is essentially insensitive to  
temperature and supply voltage variations.  
http://onsemi.com  
MARKING  
DIAGRAM  
8
1
8
D
1
LA  
Designed for 1.65 V to 5.5 V V Operation  
US8  
CC  
US SUFFIX  
CASE 493  
Over Voltage Tolerant Inputs and Outputs  
LVTTL Compatible − Interface Capability with 5 V TTL Logic  
with V = 3 V  
CC  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
LA = Device Code  
D = Date Code  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
Current Drive Capability is 24 mA at the Outputs  
PIN ASSIGNMENT  
Chip Complexity: FET = 94  
1
2
IN A1  
OUT Y3  
IN A2  
3
4
5
IN A1  
1
2
8
7
V
CC  
GND  
OUT Y2  
IN A3  
OUT Y3  
OUT Y1  
IN A3  
6
7
8
OUT Y1  
V
CC  
IN A2  
GND  
3
4
6
5
FUNCTION TABLE  
OUT Y2  
A Input  
Y Output  
L
H
L
H
Figure 1. Pinout (Top View)  
IN A1  
OUT Y1  
ORDERING INFORMATION  
IN A2  
IN A3  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
OUT Y2  
OUT Y3  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
March, 2004 − Rev. 3  
NL37WZ14/D  

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