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NL37WZ17/D

更新时间： 2024-09-24 23:53:51

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	91K
描述
Triple Noninverting Schmitt-Trigger Buffer

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NL37WZ17/D 数据手册

NL37WZ17

Triple Noninverting

Schmitt−Trigger Buffer

The NL37WZ17 is a high performance buffer with Schmitt-Trigger

inputs operating from a 1.65 to 5.5 V supply.

The NL37WZ17 can be used as a line receiver which will receive

slow input signals. The NL37WZ17 is capable of transforming slowly

changing input signals into sharply defined, jitter-free output signals.

In addition, it has a greater noise margin than conventional inverters.

The NL37WZ17 has hysteresis between the positive-going and the

negative-going input thresholds (typically 1.0 V) which is determined

internally by transistor ratios and is essentially insensitive to

temperature and supply voltage variations.

http://onsemi.com

MARKING

DIAGRAM

• Designed for 1.65 V to 5.5 V V Operation

• Over Voltage Tolerant Inputs and Outputs

• LVTTL Compatible - Interface Capability with 5 V TTL Logic

US8

US SUFFIX

CASE 493

with V = 3 V

• LVCMOS Compatible

• 24 mA Balanced Output Sink and Source Capability

D = Date Code

• Near Zero Static Supply Current Substantially Reduces System

Power Requirements

• Current Drive Capability is 24 mA at the Outputs

• Chip Complexity: FET = 94

PIN ASSIGNMENT

IN A1

OUT Y3

IN A2

GND

IN A1

OUT Y2

IN A3

OUT Y3

OUT Y1

IN A3

OUT Y1

IN A2

GND

FUNCTION TABLE

A Input

OUT Y2

Y Output

Figure 1. Pinout

ORDERING INFORMATION

IN A1

OUT Y1

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

IN A2

IN A3

OUT Y2

OUT Y3

Figure 2. Logic Symbol

Semiconductor Components Industries, LLC, 2003

Publication Order Number:

May, 2003 - Rev. 3

NL37WZ17/D

12 3 4 5 6 7 8

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