Datasheet > NL37WZ17_06

NL37WZ17_06

更新时间： 2024-11-13 03:46:23

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
6页	70K
描述
Triple Noninverting Schmitt-Trigger Buffer

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NL37WZ17_06 数据手册

NL37WZ17

Triple Noninverting

Schmitt−Trigger Buffer

The NL37WZ17 is a high performance buffer with Schmitt−Trigger

inputs operating from a 1.65 to 5.5 V supply.

The NL37WZ17 can be used as a line receiver which will receive

slow input signals. The NL37WZ17 is capable of transforming slowly

changing input signals into sharply defined, jitter−free output signals.

In addition, it has a greater noise margin than conventional inverters.

The NL37WZ17 has hysteresis between the positive−going and the

negative−going input thresholds (typically 1.0 V) which is determined

internally by transistor ratios and is essentially insensitive to

temperature and supply voltage variations.

http://onsemi.com

MARKING

DIAGRAM

US8

LX M G

US SUFFIX

CASE 493

Features

• Designed for 1.65 V to 5.5 V V Operation

• Over Voltage Tolerant Inputs and Outputs

• LVTTL Compatible − Interface Capability with 5 V TTL Logic

= Device Code

= Date Code*

= Pb−Free Package

with V = 3 V

• LVCMOS Compatible

• 24 mA Balanced Output Sink and Source Capability

• Near Zero Static Supply Current Substantially Reduces System

Power Requirements

(Note: Microdot may be in either location)

*Date Code orientation may vary depending upon

manufacturing location.

• Current Drive Capability is 24 mA at the Outputs

• Chip Complexity: FET = 94

• Pb−Free Package is Available

PIN ASSIGNMENT

IN A1

OUT Y3

IN A2

GND

IN A1

OUT Y2

IN A3

OUT Y3

OUT Y1

IN A3

OUT Y1

IN A2

GND

FUNCTION TABLE

A Input

OUT Y2

Y Output

Figure 1. Pinout

IN A1

OUT Y1

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

IN A2

IN A3

OUT Y2

OUT Y3

Figure 2. Logic Symbol

Publication Order Number:

April, 2006 − Rev. 5

NL37WZ17/D

12 3 4 5 6

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