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NL37WZ17USG PDF预览

NL37WZ17USG

更新时间: 2024-02-09 15:19:59
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 70K
描述
Triple Noninverting Schmitt-Trigger Buffer

NL37WZ17USG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:LEAD FREE, US-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.3
Is Samacsys:N系列:37WZ
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:2.3 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.024 A
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP8,.12,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:6.6 ns传播延迟(tpd):7.4 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:0.9 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:2 mm
Base Number Matches:1

NL37WZ17USG 数据手册

 浏览型号NL37WZ17USG的Datasheet PDF文件第2页浏览型号NL37WZ17USG的Datasheet PDF文件第3页浏览型号NL37WZ17USG的Datasheet PDF文件第4页浏览型号NL37WZ17USG的Datasheet PDF文件第5页浏览型号NL37WZ17USG的Datasheet PDF文件第6页 
NL37WZ17  
Triple Noninverting  
Schmitt−Trigger Buffer  
The NL37WZ17 is a high performance buffer with Schmitt−Trigger  
inputs operating from a 1.65 to 5.5 V supply.  
The NL37WZ17 can be used as a line receiver which will receive  
slow input signals. The NL37WZ17 is capable of transforming slowly  
changing input signals into sharply defined, jitter−free output signals.  
In addition, it has a greater noise margin than conventional inverters.  
The NL37WZ17 has hysteresis between the positive−going and the  
negative−going input thresholds (typically 1.0 V) which is determined  
internally by transistor ratios and is essentially insensitive to  
temperature and supply voltage variations.  
http://onsemi.com  
MARKING  
DIAGRAM  
8
8
1
US8  
LX M G  
US SUFFIX  
CASE 493  
Features  
G
Designed for 1.65 V to 5.5 V V Operation  
CC  
Over Voltage Tolerant Inputs and Outputs  
1
LVTTL Compatible − Interface Capability with 5 V TTL Logic  
LX  
M
G
= Device Code  
= Date Code*  
= Pb−Free Package  
with V = 3 V  
CC  
LVCMOS Compatible  
24 mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current Substantially Reduces System  
Power Requirements  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending upon  
manufacturing location.  
Current Drive Capability is 24 mA at the Outputs  
Chip Complexity: FET = 94  
Pb−Free Package is Available  
PIN ASSIGNMENT  
1
2
IN A1  
OUT Y3  
3
4
IN A2  
GND  
IN A1  
1
2
8
7
V
CC  
5
6
OUT Y2  
IN A3  
OUT Y3  
OUT Y1  
IN A3  
7
8
OUT Y1  
V
CC  
IN A2  
GND  
3
4
6
5
FUNCTION TABLE  
A Input  
OUT Y2  
Y Output  
L
L
H
H
Figure 1. Pinout  
1
1
IN A1  
OUT Y1  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
IN A2  
IN A3  
OUT Y2  
OUT Y3  
1
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
April, 2006 − Rev. 5  
NL37WZ17/D  

NL37WZ17USG 替代型号

型号 品牌 替代类型 描述 数据表
NL37WZ17US ONSEMI

完全替代

Triple Noninverting Schmitt-Trigger Buffer
NC7NZ17K8X ONSEMI

类似代替

带施密特触发器输入的TinyLogic UHS三通道缓冲器
SN74LVC3G17DCUR TI

功能相似

TRIPLE SCHMITT TRIGGER BUFFER

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