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MTP3055

更新时间: 2024-10-31 22:45:47
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摩托罗拉 - MOTOROLA /
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8页 163K
描述
TMOS POWER FET 12 AMPERES 60 VOLTS RDS(on) = 0.15 OHM

MTP3055 数据手册

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Order this document  
by MTP3055V/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
N–Channel Enhancement–Mode Silicon Gate  
TMOS POWER FET  
12 AMPERES  
60 VOLTS  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
R
= 0.15 OHM  
DS(on)  
TM  
New Features of TMOS V  
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
D
DS(on)  
Faster Switching than E–FET Predecessors  
Features Common to TMOS V and TMOS E–FETS  
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and  
TMOS E–FET  
G
CASE 221A–06, Style 5  
TO–220AB  
I
DSS  
DS(on)  
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
60  
Unit  
Vdc  
Vdc  
Drain–Source Voltage  
V
DSS  
Drain–Gate Voltage (R  
= 1.0 M)  
Gate–Source Voltage — Continuous  
V
DGR  
60  
GS  
V
± 20  
± 25  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous @ 25°C  
Drain Current — Continuous @ 100°C  
I
I
12  
7.3  
37  
Adc  
Apk  
D
D
Drain Current — Single Pulse (t 10 µs)  
I
p
DM  
Total Power Dissipation @ 25°C  
Derate above 25°C  
P
D
48  
0.32  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
55 to 175  
72  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V = 10 Vdc, I = 12 Apk, L = 1.0 mH, R = 25 )  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
θJC  
R
θJA  
3.13  
62.5  
°C/W  
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds  
T
L
260  
°C  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 2  
Motorola, Inc. 1996  

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