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MTB60N05HDLT4 PDF预览

MTB60N05HDLT4

更新时间: 2024-11-23 20:10:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 开关脉冲晶体管
页数 文件大小 规格书
12页 214K
描述
Power Field-Effect Transistor, 60A I(D), 50V, 0.014ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET

MTB60N05HDLT4 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SMALL OUTLINE, R-PSSO-G2Reach Compliance Code:unknown
风险等级:5.77雪崩能效等级(Eas):540 mJ
外壳连接:DRAIN配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:50 V最大漏极电流 (Abs) (ID):60 A
最大漏极电流 (ID):60 A最大漏源导通电阻:0.014 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G2
JESD-609代码:e0元件数量:1
端子数量:2工作模式:ENHANCEMENT MODE
最高工作温度:175 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):150 W
最大脉冲漏极电流 (IDM):180 A认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子位置:SINGLE晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

MTB60N05HDLT4 数据手册

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Order this document  
by MTB60N05HDL/D  
SEMICONDUCTOR TECHNICAL DATA  
Motorola Preferred Device  
TMOS POWER FET  
60 AMPERES  
50 VOLTS  
N–Channel Enhancement–Mode Silicon Gate  
2
The D PAK package has the capability of housing a larger die  
R
= 0.014 OHM  
DS(on)  
than any existing surface mount package which allows it to be used  
in applications that require the use of surface mount components  
with higher power and lower R  
capabilities. This advanced  
DS(on)  
high–cell density HDTMOS power FET is designed to withstand  
high energy in the avalanche and commutation modes. This new  
energy efficient design also offers a drain–to–source diode with a  
fast recovery time. Designed for low voltage, high speed switching  
applications in power supplies, converters and PWM motor  
controls, these devices are particularly well suited for bridge circuits  
where diode speed and commutating safe operating areas are  
critical and offer additional safety margin against unexpected  
voltage transients.  
D
G
Avalanche Energy Specified  
Source–to–Drain Diode Recovery Time Comparable to a  
Discrete Fast Recovery Diode  
CASE 418B–03, Style 2  
2
D PAK  
S
Diode is Characterized for Use in Bridge Circuits  
I
and V  
Specified at Elevated Temperature  
DSS  
DS(on)  
Short Heatsink Tab Manufactured — Not Sheared  
Specially Designed Leadframe for Maximum Power Dissipation  
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4  
Suffix to Part Number  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
C
Rating  
Symbol  
Value  
50  
Unit  
Vdc  
Vdc  
Drain–to–Source Voltage  
V
DSS  
Drain–to–Gate Voltage (R  
= 1.0 M)  
Gate–to–Source Voltage — Continuous  
V
DGR  
50  
GS  
V
± 15  
± 20  
Vdc  
Vpk  
GS  
Gate–Source Voltage — Non–Repetitive (t 10 ms)  
V
GSM  
p
Drain Current — Continuous  
Drain Current — Continuous @ 100°C  
Drain Current — Single Pulse (t 10 µs)  
I
I
60  
42  
180  
Adc  
Apk  
D
D
I
p
DM  
Total Power Dissipation  
Derate above 25°C  
P
D
150  
1.0  
Watts  
W/°C  
Operating and Storage Temperature Range  
T , T  
stg  
– 55 to 175  
540  
°C  
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V  
= 10 Vdc, Peak I = 60 Apk, L = 0.3 mH, R = 25 Ω)  
GS L G  
Thermal Resistance — Junction to Case  
Thermal Resistance — Junction to Ambient  
R
R
1.0  
62.5  
°C/W  
°C  
θJC  
θJA  
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 5 seconds  
T
260  
L
E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Thermal Clad is a trademark of the Bergquist Company.  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
Preferred devices are Motorola recommended choices for future use and best overall value.  
REV 1  
Motorola, Inc. 1999  

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