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by MTB75N05HD/D
SEMICONDUCTOR TECHNICAL DATA
Motorola Preferred Device
TMOS POWER FET
75 AMPERES
50 VOLTS
N–Channel Enhancement–Mode Silicon Gate
2
The D PAK package has the capability of housing a larger die
R
= 9.5 mΩ
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
DS(on)
with higher power and lower R
capabilities. This advanced
DS(on)
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
D
•
•
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
G
CASE 418B–03, Style 2
2
D PAK
S
•
•
•
•
•
Diode is Characterized for Use in Bridge Circuits
I
and V
Specified at Elevated Temperature
DSS
DS(on)
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Symbol
Value
50
Unit
Drain–to–Source Voltage
V
DSS
Volts
Drain–to–Gate Voltage (R
GS
= 1.0 MΩ)
V
DGR
50
Gate–to–Source Voltage — Continuous
V
GS
± 20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (t ≤ 10 µs)
I
I
75
65
225
Amps
D
D
I
p
DM
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T = 25°C (minimum footprint, FR–4 board)
P
D
125
1.0
2.5
Watts
W/°C
Watts
A
Operating and Storage Temperature Range
T , T
stg
– 55 to 150
500
°C
J
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C
E
AS
mJ
J
(V
DD
= 25 V, V
= 10 V, Peak I = 75 A, L = 0.177 mH, R = 25 Ω)
GS L G
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (minimum footprint, FR–4 board)
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
T
L
260
°C
Thisdatasheetpermitsthedesignofmostcircuitsentirelyfromtheinformationpresented.SOALimitcurves — representingboundariesondevicecharacteristics — are
given to facilitate “worst case” design.
E–FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola TMOS Power MOSFET Transistor Device Data
1
Motorola, Inc. 1999