CMOS ST-BUSTM Family
MT89L86
Multiple Rate Digital Switch
Data Sheet
January 2006
Features
•
•
•
•
•
3.3 volt supply
Ordering Information
5 V tolerant inputs and TTL compatible outputs
256 x 256 or 512 x 256 switching configurations
8-bit or 4-bit channel switching capability
MT89L86AP
44 Pin PLCC
48 Pin SSOP
48 Pin SSOP
44 Pin PLCC
48 Pin SSOP*
48 Pin SSOP*
44 Pin PLCC*
44 Pin PLCC*
Tubes
MT89L86AN
Tubes
MT89L86ANR
MT89L86APR
MT89L86AN1
MT89L86ANR1
MT89L86AP1
MT89L86APR1
Tape & Reel
Tape & Reel
Tubes
Guarantees frame integrity for wideband
Tape & Reel
Tubes
channels
Tape & Reel
•
•
Automatic identification of ST-BUS/GCI interfaces
*Pb Free Matte Tin
Accepts serial streams with data rates of 2.048,
-40°C to +85°C
4.096 or 8.192 Mb/s
•
Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
Programmable frame offset on inputs
Per-channel three-state control
Per-channel message mode
•
•
•
Centralized voice processing systems
Voice/Data multiplexer
•
•
•
•
ADPCM 32 kbit/s channel switching
Description
The 3.3 V Multiple Rate Digital Switch (MT89L86) is
pin compatible with Zarlink’s 5 V MT8986 and retains
all of its functionality. This 3.3 V device is designed to
provide simultaneous non-blocking connections for up
to 256 64 kb/s channels or blocking connections for up
to 512 64 kb/s channels. The serial inputs and outputs
may have 32 to 128 64 kb/s channels per frame with
data rates ranging from 2048 up to 8192 kb/s. It also
provides per-channel selection between variable and
constant throughput delays allowing voice and
grouped data channels to be switched without
corrupting the data sequence integrity.
Control interface compatible to Intel/Motorola
CPUs
•
Low power consumption
Applications
•
Medium size mixed voice and data
switching/processing matrices
•
•
•
Hyperchannel switching (e.g., ISDN H0)
MVIP™ interface functions
Serial bus control and monitoring
**
V
V
ODE
DD
SS
RESET
STi0
STi1
Output
MUX
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
Multiple Buffer Data
Memory
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
Serial
to
Parallel
Converter
Parallel
to
Serial
Internal Registers
Converter
Timing
Unit
Connection
Memory
Microprocessor
STi15
Interface
CLK FR AS/ IM DS
A0/
A7
AD7/
AD0
CSTo
CS R/W
WR
DTA
ALE
RD
** for 48-pin SSOP only
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.