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MT58L512V18PS-6IT PDF预览

MT58L512V18PS-6IT

更新时间: 2024-11-09 15:45:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
32页 614K
描述
Cache SRAM, 512KX18, 3.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT58L512V18PS-6IT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.22最长访问时间:3.5 ns
其他特性:AUTOMATIC POWER DOWN; SELF-TIMED WRITE CYCLE; INDIVIDUAL BYTE WRITEJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:9437184 bit内存集成电路类型:CACHE SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:100
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MT58L512V18PS-6IT 数据手册

 浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第2页浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第3页浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第4页浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第5页浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第6页浏览型号MT58L512V18PS-6IT的Datasheet PDF文件第7页 
8Mb: 512K x 18, 256K x 32/36  
PIPELINED, SCD SYNCBURST SRAM  
8Mb SYNCBURST™  
SRAM  
MT58L512L18P, MT58L256L32P, MT58L256L36P;  
MT58L512V18P, MT58L256V32P, MT58L256V36P  
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle  
Deselect  
FEATURES  
1
100-Pin TQFP  
• Fast clock and OE# access times  
• Single +3.3V +0.3V/-0.165V power supply (VDD)  
• Separate +3.3V or +2.5V isolated output buffer  
supply (VDDQ)  
• SNOOZE MODE for reduced-power standby  
• Single-cycle deselect (Pentium® BSRAM-compatible)  
• Common data inputs and data outputs  
• Individual BYTE WRITE control and GLOBAL  
WRITE  
• Three chip enables for simple depth expansion  
and address pipelining  
• Clock-controlled and registered addresses, data  
I/Os and control signals  
• Internally self-timed WRITE cycle  
• Burst control (interleaved or linear burst)  
• Automatic power-down for portable applications  
• 100-pin TQFP package  
165-Pin FBGA  
(Preliminary Package Data)  
• 165-pin FBGA package  
• 119-pin BGA package  
• Low capacitive bus loading  
• x18, x32, and x36 versions available  
OPTIONS  
MARKING*  
• Timing (Access/Cycle/MHz)  
3.1ns/5ns/200 MHz  
3.5ns/6ns/166 MHz  
4.0ns/7.5ns/133 MHz  
5ns/10ns/100 MHz  
• Configurations  
3.3V I/O  
-5  
-6  
-7.5  
-10  
2
119-Pin BGA  
512K x 18  
256K x 32  
256K x 36  
MT58L512L18P  
MT58L256L32P  
MT58L256L36P  
2.5V I/O  
512K x 18  
256K x 32  
256K x 36  
MT58L512V18P  
MT58L256V32P  
MT58L256V36P  
• Packages  
100-pin TQFP (2-chip enable)  
100-pin TQFP (3-chip enable)  
165-pin, 13mm x 15mm FBGA  
119-pin, 14mm x 22mm BGA  
• Operating Temperature Range  
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)**  
T
S
F
B
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).  
2. JEDEC-standard MS-028 BHA (PBGA).  
Part Number Example:  
None  
IT  
MT58L512L18PT-6  
* A Part Marking Guide for the FBGA devices can be found on Micron’s  
web site—http://www.micron.com/support/index.html.  
**Industrial temperature range offered in specific speed grades and  
confgurations. Contact factory for more information.  
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM  
MT58L512L18P_2.p65 – Rev. 6/01  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1
©2001, Micron Technology, Inc.  

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