Datasheet > MT58L512Y36FT-10

MT58L512Y36FT-10

更新时间： 2024-11-08 08:25:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
34页	537K
描述
Cache SRAM, 512KX36, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100

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中文翻译

获取价格

数据手册

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MT58L512Y36FT-10 数据手册

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH SYNCBURST SRAM

MT58L1MY18F, MT58V1MV18F,

MT58L512Y32F, MT58V512V32F,

MT58L512Y36F, MT58V512V36F

3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O

18Mb SYNCBURST^™

SRAM

Features

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

•

Fast clock and OE# access times

Single 3.3V ±± percent or 2.±V ±± percent power supply

Separate 3.3V±± percent or 2.±V ±± percent isolated

output buffer supply (VDDQ)

•

SNOOZE MODE for reduced-power standby

Common data inputs and data outputs

Individual byte write control and global write

Three chip enables for simple depth expansion and

address pipelining

•

Clock-controlled and registered addresses, data

I/Os, and control signals

•

Internally self-timed write cycle

Burst control (interleaved or linear burst)

Low capacitive bus loading

Figure 2: 165-Ball FBGA

JEDEC-Standard MO-216 (Var. CAB-1)

TQFP

Marking

Options

•

Timing (Access/Cycle/MHz)

6.8ns/7.±ns/133 MHz

7.±ns/8.8ns/113 MHz

8.±ns/10ns/100 MHz

10ns/1±ns/66 MHz

-6.8

-7.±

-8.±

-10

•

Configurations

3.3V VDD, 3.3V or 2.±V I/O

1 Meg x 18

±12K x 32

±12K x 36

MT±8L1MY18F

MT±8L±12Y32F

MT±8L±12Y36F

Part Number Example:

MT58L512Y36FT-10

2.±V VDD, 2.±V I/O

1 Meg x 18

±12K x 32

±12K x 36

MT±8V1MV18F

MT±8V±12V32F

MT±8V±12V36F

General Description

The Micron^®SyncBurst™ SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

•

Packages

100-pin TQFP

16±-ball, 13mm x 1±mm FBGA

F¹

Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x

18, ±12K x 32, or ±12K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

(CE#), two additional chip enables for easy depth

expansion (CE2#, CE2), burst control inputs (ADSC#,

ADSP#, ADV#), byte write enables (BWx#), and global

write (GW#).

Operating Temperature Range

Commercial (0ºC

Industrial (-40ºC

+70ºC)

+8±ºC)

None

IT²

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact factory for availability of Industrial Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM

MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

12 3 4 5 6 7...34

中文翻译

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与MT58L512Y36FT-10相关器件

型号	品牌	获取价格	描述	数据表
MT58L512Y36FT-6.8	CYPRESS	获取价格	Cache SRAM, 512KX36, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L512Y36FT-7.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36FT-8.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36PF-10	ROCHESTER	获取价格	512KX36 CACHE SRAM, 5ns, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36PF-5	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36PF-6	ROCHESTER	获取价格	512KX36 CACHE SRAM, 3.5ns, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36PT-5	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36PT-6	ROCHESTER	获取价格	512KX36 CACHE SRAM, 3.5ns, PQFP100, PLASTIC, TQFP-100
MT58L64L18DT-10	ROCHESTER	获取价格	64K X 18 CACHE SRAM, 5 ns, PQFP100, PLASTIC, TQFP-100
MT58L64L18DT-7.5	ROCHESTER	获取价格	64K X 18 CACHE SRAM, 4.2 ns, PQFP100, PLASTIC, TQFP-100

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