Datasheet > MT58L512Y36D

MT58L512Y36D

更新时间： 2024-09-16 22:10:31

品牌	Logo	应用领域
镁光 - MICRON		静态存储器
页数	文件大小	规格书
34页	524K
描述
16Mb SYNCBURST⑩ SRAM

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中文翻译

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数据手册

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MT58L512Y36D 数据手册

ADVANCE

16Mb : 1 MEG x 18, 512K x 32/36

PIPELINED, DCD SYNCBURST SRAM

16Mb SYNCBURST^™

SRAM

MT58L1MY18D, MT58V1MV18D,

MT58L512Y32D, MT58V512V32D,

MT58L512Y36D, MT58V512V36D

3.3V VDD, 3.3V o r 2.5V I/O; 2.5V VDD, 2.5V

I/O, Pip e lin e d , Do u b le -Cycle De se le ct

FEATURES

• Fast clock an d OE# access tim es

• Sin gle +3.3V ±0.165Vor 2.5V ±0.125V power supply

(V^DD)

100-Pin TQFP

• Separate +3.3V or 2.5V isolated output buffer

supply (VDDQ)

• SNOOZE MODE for reduced-power stan dby

• Com m on data in puts an d data outputs

• In dividual BYTE WRITE con trol an d GLOBAL

WRITE

• Th ree ch ip en ables for sim ple depth expan sion an d

address pipelin in g

• Clock-con trolled an d registered addresses, data I/Os

an d con trol sign als

• In tern ally self-tim ed WRITE cycle

• Burst con trol (in terleaved or lin ear burst)

• Autom atic power-down

165-Pin FBGA

(Preliminary Package Data)

• 100-pin TQFP package

• 165-pin FBGA package

• Low capacitive bus loadin g

• x18, x32, an d x36 version s available

OPTIONS

TQFP MARKING*

• Tim in g (Access/Cycle/MHz)

3.5n s/6n s/166 MHz

4.0n s/7.5n s/133 MHz

5n s/10n s/100 MHz

-6

-7.5

-10

NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).

• Con figuration s

3.3V VDD, 3.3V or 2.5V I/O

1 Meg x 18

MT58L1MY18D

MT58L512Y32D

MT58L512Y36D

GENERAL DESCRIPTION

Th e Micron ^®Syn cBurst^™SRAM fam ily em ploys h igh -

speed, low-power CMOS design s th at are fabricated

usin g an advan ced CMOS process.

512K x 32

512K x 36

2.5V VDD, 2.5V I/O

1 Meg x 18

MT58V1MV18D

MT58V512V32D

MT58V512V36D

Micron ’s 16Mb Syn cBurst SRAMs in tegrate a 1 Meg x

18, 512K x 32, or 512K x 36 SRAM core with advan ced

syn ch ron ous periph eral circuitry an d a 2-bit burst

coun ter. All syn ch ron ous in puts pass th rough registers

con trolled by a positive-edge-triggered sin gle-clock in -

put (CLK). Th e syn ch ron ous in puts in clude all addresses,

all data in puts, active LOW ch ip en able (CE#), two

addition al ch ip en ables for easy depth expan sion (CE2,

CE2#), burst con trol in puts (ADSC#, ADSP#, ADV#),

byte write en ables (BWx#) an d global write (GW#). Note

th at CE2# is n ot available on th e T Version .

512K x 32

512K x 36

• Packages

100-pin TQFP (3-ch ip en able)

165-pin FBGA

• Operatin g Tem perature Ran ge

Com m ercial (0ºC to +70ºC)

Non e

*See page 34 for FBGA package m arkin g guide.

Asyn ch ron ous in puts in clude th e output en able

(OE#), clock (CLK) an d sn ooze en able (ZZ). Th ere is also

Part Number Example:

MT58L1MY18DT-7.5

16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM

MT58L1MY18D_2.p65 – Rev 7/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12 3 4 5 6 7...34

中文翻译

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与MT58L512Y36D相关器件

型号	品牌	获取价格	描述	数据表
MT58L512Y36FF-6.8	CYPRESS	获取价格	Cache SRAM, 512KX36, 6.8ns, CMOS, PBGA165, MO-216CAB-1, FBGA-165
MT58L512Y36FF-7.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36FF-8.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36FT-10	CYPRESS	获取价格	Cache SRAM, 512KX36, 10ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36FT-6.8	CYPRESS	获取价格	Cache SRAM, 512KX36, 6.8ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
MT58L512Y36FT-7.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36FT-8.5	CYPRESS	获取价格	Cache SRAM, 512KX36, 8.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
MT58L512Y36PF-10	ROCHESTER	获取价格	512KX36 CACHE SRAM, 5ns, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36PF-5	CYPRESS	获取价格	Cache SRAM, 512KX36, 3.1ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
MT58L512Y36PF-6	ROCHESTER	获取价格	512KX36 CACHE SRAM, 3.5ns, PBGA165, 13 X 15 MM, FBGA-165

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