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MT46H16M16LF PDF预览

MT46H16M16LF

更新时间: 2024-11-18 04:14:19
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率
页数 文件大小 规格书
3页 113K
描述
Mobile Double Data Rate (DDR) SDRAM

MT46H16M16LF 数据手册

 浏览型号MT46H16M16LF的Datasheet PDF文件第2页浏览型号MT46H16M16LF的Datasheet PDF文件第3页 
Preview  
256Mb: 16 Meg x 16, 8 Meg x 32 Mobile DDR SDRAM  
Mobile Double Data Rate (DDR) SDRAM  
MT46H16M16LF – 4 Meg x 16 x 4 Banks  
MT46H8M32LF – 2 Meg x 32 x 4 Banks  
For a complete data sheet, please refer to www.micron.com/mobileds.  
Figure 1: 60-Ball VFBGA Assignment  
Features  
VDD = +1.8V ±±.1V, VDDQ = +1.8V ±±.1V  
Bidirectional data strobe per byte of data (DQS)  
Internal, pipelined double data rate (DDR)  
architecture; two data accesses per clock cycle  
Differential clock inputs (CK and CK#)  
Commands entered on each positive CK edge  
DQS edge-aligned with data for READs; center-  
aligned with data for WRITEs  
1
2
3
4
5
6
7
8
9
A
B
C
D
E
VSS  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VSS  
DQ15  
VSSQ  
VDDQ  
DQ1  
DQ3  
DQ5  
DQ7  
DQ0  
DQ2  
DQ4  
DQ6  
LDQS  
VDD  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VDD  
DQ13 DQ14  
DQ11 DQ12  
Four internal banks for concurrent operation  
Data masks (DM) for masking write data–one mask  
per byte  
DQ9  
UDQS  
UDM  
CK  
DQ10  
DQ8  
NC  
Programmable burst lengths: 2, 4, 8, 16 or full page  
Concurrent auto precharge option is supported  
Auto refresh and self refresh modes  
1.8V LVCMOS compatible inputs  
On-chip temperature sensor to control refresh rate  
Partial array self refresh (PASR)  
Deep power-down (DPD)  
Selectable output drive (DS)  
Clock stop capability  
F
A13, NC LDM  
G
H
J
CKE  
A9  
CK#  
A12  
A8  
WE#  
CS#  
CAS#  
BA0  
A0  
RAS#  
BA1  
A11  
A7  
A6  
A10/AP  
A2  
A1  
K
VSS  
A4  
A5  
A3  
VDD  
Options  
Marking  
VDD/VDDQ  
1.8V/1.8V  
Configuration  
Table 1: Configuration Addressing  
H
Architecture  
16 Meg x 16  
8 Meg x 32  
16 Meg x 16 (4 Meg x 16 x 4 banks)  
8 Meg x 32 (2 Meg x 32 x 4 banks)  
16M16  
8M32  
4 Meg x 16 x 4  
8K  
2 Meg x 32 x 4  
4K  
Configuration  
Plastic Package  
Refresh Count  
1
6±-Ball VFBGA  
TBD  
8K (A0–A12)  
4 (BA0, BA1)  
1K (A0–A9)  
4K (A0–A11)  
4 (BA0, BA1)  
1K (A0–A9)  
Row Addressing  
Bank Addressing  
Column Addressing  
2
9±-Ball VFBGA  
Timing – Cycle Time  
6ns @ CL = 3  
7.5ns @ CL = 3  
1±ns @ CL = 3  
-6  
-75  
-1±  
Operating Temperature Range  
Commercial (±° to +7±°C)  
Industrial (-4±°C to +85°C)  
None  
IT  
Notes:1. Only available for x16 configuration.  
2. Only available for x32 configuration.  
PDF: 09005aef818ff781/Source: 09005aef818ff799  
MT46H16M16.fm - Rev. A 03/05 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2005 Micron Technology, Inc. All rights reserved.  
1
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron  
to meet Micron’s production data sheet specifications.  

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