512Mb: x16, x32 Automotive LPDDR SDRAM
Features
Automotive LPDDR SDRAM
MT46H32M16LF – 8 Meg x 16 x 4 banks
MT46H16M32LF – 4 Meg x 32 x 4 banks
MT46H16M32LG – 4 Meg x 32 x 4 banks
Options
Marking
Features
• VDD/VDDQ = 1.70–1.95V
• VDD/VDDQ
– 1.8V/1.8V
• Configuration
H
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
– 16 Meg x 32 (4 Meg x 32 x 4 banks)
• Addressing
– JEDEC-standard addressing
• Plastic "green" package
– 60-ball VFBGA (8mm x 9mm)1
– 90-ball VFBGA (8mm x 13mm)2
– 90-ball VFBGA (8mm x 13mm)2
• Timing – cycle time
32M16
16M32
• Differential clock inputs (CK and CK#)
LF
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
BF
B5
BQ
• 4 internal banks for concurrent operation
• Data masks (DM) for masking write data; one mask
per byte
– 5ns @ CL = 3 (200 MHz)
– 6ns @ CL = 3 (166 MHz)
• Power
-5
-6
• Programmable burst lengths (BL): 2, 4, 8, or 16
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• Temperature-compensated self refresh (TCSR)
• Partial-array self refresh (PASR)
– Standard IDD2/IDD6
None
L
– Low-power IDD2/IDD6
• Product certification
– Automotive
• Operating temperature range
– Industrial (–40˚C to +85˚C)
– Automotive (–40˚C to +105˚C)
• Design revision
A
• Deep power-down (DPD)
IT
AT
:C
• Status read register (SRR)
• Selectable output drive strength (DS)
• Clock stop capability
1. Only available for x16 configuration.
2. Only available for x32 configuration.
Notes:
• 64ms refresh, 32ms for automotive temperature
Table 1: Key Timing Parameters (CL = 3)
Speed Grade
Clock Rate
200 MHz
Access Time
5.0ns
-5
-6
166 MHz
5.0ns
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t67m_embedded_lpddr_512mb.pdf - Rev. E 05/18 EN
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© 2012 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.