ADVANCE‡
512Mb: x4, x8, x16
DDR SDRAM
MT46V128M4 –32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
DOUBLE DATA RATE
(DDR) SDRAM
For the latest data sheet revisions, please refer to the Micron
Website:www.micron.com/datasheets
FEATURES
• VDD = +2.5V ±±.2Vꢀ VDDQ = +2.5V ±±.2V
• Bidirectional data strobe (DQS) transmitted/
received with dataꢀ i.e.ꢀ source-synchronous data
capture (x16 has two – one per byte)
PINASSIGNMENT(TOPVIEW)
66-PinTSOP
x8
x4
x4
x8
x16
x16
• Internalꢀ pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• Programmable burst lengths: 2ꢀ 4ꢀ or 8
• x16 has programmable IOL/IOV.
• Concurrent auto precharge option is supported
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
V
NC
DD
DD
V
DQ7
V
NC
DQ6
V
NC
DQ5
V
NC
DQ4
V
NC
NC
V
DQS
DNU
V
V
DM
CK#
CK
CKE
NC
SS
VSS
V
DQ0
DD
DD
V
DQ0
DD
DD
1
2
3
4
5
6
7
8
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
V
Q
SS
Q
V
Q
V
Q
NC
DQ0
NC
DQ1
DQ1
DQ2
VssQ
DQ3
DQ4
V
SS
Q
DD
Q
VSS
Q
NC
NC
NC
DQ2
V
DD
Q
SS
Q
V
DD
Q
V
DD
Q
9
NC
DQ1
NC
DQ3
DQ5
DQ6
VssQ
DQ7
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
V
SS
Q
DD
Q
V
SS
Q
NC
NC
NC
NC
V
DD
Q
NC
NC
SS
Q
V
DD
Q
V
DD
Q
NC LDQS
NC NC
V
DD
REF
V
V
REF
VDD
V
DD
DNU
LDM
WE#
CAS#
RAS#
CS#
V
V
REF
DNU
NC
WE#
CAS#
RAS#
CS#
SS
SS
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
NC
BA0
BA1
BA0
BA1
A10/AP
A0
OPTIONS
• Configuration
MARKING
A10/AP A10/AP
A0
A1
A2
A3
A0
A1
A2
A3
A1
A2
A3
128 Meg x 4 (32 Meg x 4 x 4 banks)
128M4
64M8
32M16
64 Meg x 8
(16 Meg x 8 x 4 banks)
(8 Meg x 16 x 4 banks)
A4
VSS
A4
VSS
VDD
SS
VDD
V
DD
32 Meg x 16
• Plastic Package – OCPL
66-pin TSOP (standard 22.3mm length) TG
(4±± mil widthꢀ ±.65mm pin pitch)
• Timing – Cycle Time
128 Meg x 4
64 Meg x 8
32 Meg x 16
Configuration
RefreshCount
32 Meg x 4 x 4 banks
8K
16Megx8x4banks 8Megx16x4banks
8K
8K
7.5ns @ CL = 2 (DDR266B)1
7.5ns @ CL = 2.5 (DDR266B)2
1±ns @ CL = 2 (DDR2±±)2
• Self Refresh
-75Z
-75
-8
RowAddressing
BankAddressing
ColumnAddressing
8K(A0–A12)
8K(A0–A12)
4(BA0,BA1)
2K(A0–A9, A11)
8K(A0–A12)
4(BA0,BA1)
1K(A0–A9)
4(BA0,BA1)
4K(A0–A9,A11,A12)
Standard
Low Power
none
L
KEYTIMINGPARAMETERS
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
SPEED
CLOCK RATE
DATA-OUT ACCESS
WINDOW* WINDOW
DQS-DQ
SKEW
GRADE
CL = 2**
CL = 2.5**
-75
-75
-8
133MHz
100MHz
100MHz
133MHz
133MHz
125MHz
2.5ns
2.5ns
3.4ns
0.75ns +0.5ns
0.75ns +0.5ns
0.8ns
+0.6ns
*Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001,MicronTechnology,Inc.
1
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTIONDATASHEETSPECIFICATIONS.
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