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MT46H16M16LFBF-6ITH PDF预览

MT46H16M16LFBF-6ITH

更新时间: 2024-11-18 12:27:51
品牌 Logo 应用领域
镁光 - MICRON 电子动态存储器双倍数据速率
页数 文件大小 规格书
79页 3101K
描述
Mobile DDR SDRAM MT46H16M16LF – 4 Meg x 16 x 4 banks MT46H8M32LF/LG – 2 Meg x 32 x 4 banks

MT46H16M16LFBF-6ITH 数据手册

 浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第2页浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第3页浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第4页浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第5页浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第6页浏览型号MT46H16M16LFBF-6ITH的Datasheet PDF文件第7页 
256Mb : x16, x32 Mo b ile DDR SDRAM  
Fe a t u re s  
Mo b ile DDR SDRAM  
MT46H16M16LF – 4 Me g x 16 x 4 b a n ks  
MT46H8M32LF/LG – 2 Me g x 32 x 4 b a n ks  
For the latest data sheet, refer to Microns Web site: www.micron.com  
Ta b le 2:  
Ke y Tim in g Pa ra m e t e rs  
Clo ck Ra t e (MHz)  
Fe a t u re s  
• VDD/ VDDQ = 1.70–1.95V  
Acce ss Tim e  
• Bidirectional data strobe per byte of data (DQS)  
• Internal, pipelined double data rate (DDR)  
architecture; two data accesses per clock cycle  
• Differential clock inputs (CK and CK#)  
• Commands entered on each positive CK edge  
• DQS edge-aligned with data for READs; center-  
aligned with data for WRITEs  
• Four internal banks for concurrent operation  
• Data masks (DM) for masking write data—one mask  
per byte  
Sp e e d  
Gra d e  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
-6  
83.3  
83.3  
166  
133  
6.5ns  
6.5ns  
5.0ns  
6.0ns  
-75  
Op t io n s  
• VDD/ VDDQ  
1.8V/ 1.8V  
Ma rkin g  
H
• Configuration  
• Programmable burst lengths: 2, 4, or 8  
• Concurrent auto precharge option supported  
Auto refresh and self refresh modes  
• 1.8V LVCMOS compatible inputs  
• On-chip temperature sensor to control self refresh  
rate  
• Partial-array self refresh (PASR)  
• Deep power-down (DPD)  
• Selectable output drive (DS)  
16 Meg x 16 (4 Meg x 16 x 4 banks)  
8 Meg x 32 (2 Meg x 32 x 4 banks)  
• Row size option  
16M16  
8M32  
JEDEC-standard option  
Reduced page-size option  
LF  
LG  
2
• Plastic green” packages  
60-ball VFBGA 8mm x 9mm  
1
BF  
B5  
2
90-ball VFBGA 8mm x 13mm  
• Timing – cycle time  
6ns at CL = 3  
7.5ns at CL = 3  
• Clock stop capability  
• 64ms refresh period  
-6  
-75  
• Power  
Standard  
Ta b le 1:  
Co n fig u ra t io n Ad d re ssin g  
None  
L
Low IDD2P/ IDD6  
• Operating temperature range  
Commercial (0°C to +70°C)  
Industrial (–40°C to +85°C)  
• Design revision  
DQ  
Bu s  
JEDEC-  
Re d u ce d  
Pa g e -Size  
Op t io n  
St a n d a rd  
Wid t h  
Arch it e ct u re  
Op t io n  
None  
IT  
:A  
4
4
BA0, BA1  
Number of banks  
Bank address balls  
Row address balls  
Column address balls  
Row address balls  
Column address balls  
BA0, BA1  
A0–A12  
A0–A8  
Notes: 1. Only available for x16 configuration.  
2. Only available for x32 configuration.  
x16  
x32  
A0–A11  
A0–A8  
A0–A12  
A0–A7  
PDF: 09005aef82091978 / Source: 09005aef8209195b  
MT46H16M16LF__1.fm - Rev. H 6/08 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2005 Micron Technology, Inc. All rights reserved.  
1
Products and specifications discussed herein are subject to change by Micron without notice.  

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