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MPC2605ZP66R PDF预览

MPC2605ZP66R

更新时间: 2024-10-28 22:46:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路微处理器静态存储器信息通信管理PC
页数 文件大小 规格书
30页 291K
描述
Integrated Secondary Cache for PowerPC Microprocessors

MPC2605ZP66R 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA, BGA241,19X19,50针数:241
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.53
Is Samacsys:N最长访问时间:8.5 ns
其他特性:8K X 18 TAGJESD-30 代码:S-PBGA-B241
JESD-609代码:e0长度:25 mm
内存密度:2359296 bit内存集成电路类型:CACHE TAG SRAM
内存宽度:72功能数量:1
端子数量:241字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX72封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA241,19X19,50
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:SRAMs最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:25 mm
Base Number Matches:1

MPC2605ZP66R 数据手册

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Order this document  
by MPC2605/D  
SEMICONDUCTOR TECHNICAL DATA  
MPC2605  
Product Preview  
Integrated Secondary Cache  
for PowerPC Microprocessors  
The MPC2605 is a single chip, 256KB integrated look–aside cache with  
copy–back capability designed for PowerPC applications (MPC603 and  
MPC604). Using 0.38 µm technology along with standard cell logic technology,  
the MPC2605 integrates data, tag, host interface, and least recently used (LRU)  
memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2  
cache with one, two, or four chips on a 64–bit PowerPC bus.  
ZP PACKAGE  
PBGA  
CASE 1138–01  
Single Chip L2 Cache for PowerPC  
66 MHz Zero Wait State Performance (2–1–1–1 Burst)  
Four–Way Set Associative Cache Design  
32K x 72 Data Memory Array  
8K x 18 Tag Array  
Address Parity Support  
LRU Cache Control Logic  
Copy–Back or Write–Through Modes of Operation  
Copy–Back Buffer for Improved Performance  
Single 3.3 V Power Supply  
5 V Tolerant I/O  
One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)  
Single Clock Operation  
Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)  
Supports up to Four Processors in a Shared Cache Configuration  
High Board Density 25 mm 241 PBGA Package  
BLOCK DIAGRAM  
COPY–BACK  
BUFFER  
CONTROL  
RD/WR  
A27, A28  
DH0 – DH31  
DL0 – DL31  
DP0 – DP7  
60X BUS  
INTERFACE  
8K x 72 x 4  
DATA RAM  
CONTROLLER  
AND  
BUS INTERFACE  
A0 – A31  
WAY SELECT  
RD/WR  
2K x 18 x 4  
TAG RAM  
COMPARE  
2K x 8 LRU  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 6  
2/26/98  
Motorola, Inc. 1998  

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