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MPC27T416TQ10 PDF预览

MPC27T416TQ10

更新时间： 2024-10-29 20:04:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 静态存储器内存集成电路
页数 文件大小 规格书
16页 341K
描述
Cache Tag SRAM, 16KX16, 12ns, MOS, PQFP80, TQFP-80

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中文翻译

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MPC27T416TQ10 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP80,.64SQ
针数：80Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.92最长访问时间：12 ns
其他特性：5V TTL AND 3.3V LVTTL COMPATIBLE WITH VCCQJESD-30 代码：S-PQFP-G80
JESD-609代码：e0长度：14 mm
内存密度：262144 bit内存集成电路类型：CACHE TAG SRAM
内存宽度：16功能数量：1
端口数量：1端子数量：80
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16KX16
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3/5,5 V
认证状态：Not Qualified座面最大高度：1.74 mm
最大待机电流：0.025 A子类别：SRAMs
最大压摆率：0.29 mA最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：MOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

MPC27T416TQ10 数据手册

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Order this document  
by MPC27T416/D  
SEMICONDUCTOR TECHNICAL DATA  
MPC27T416  
Advance Information  
16K x 16 Bit Cache Tag RAM  
for PowerPC Processors  
The MPC27T416 is a 262,144 bit cache–tag static RAM designed to support  
PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K  
words of 16 bits each and is fabricated using Motorola‘s high performance, silicon  
gate BiCMOS technology. There are fourteen common I/O tag bits and two separate  
I/O status bits. A 14–bit comparator is on–chip to allow fast comparison of the 14  
stored tag bits with the current tag input data. An active high MATCH output is  
generated when the valid bit is true and these two groups of data are the same for  
a given address.  
TQ PACKAGE  
TQFP  
CASE 917A–02  
This high–speed MATCH signal, with t  
fastest possible enabling of secondary cache accesses.  
times as fast as 9 ns, provides the  
AVMV  
The two separate I/O status bits (VALID, DIRTY) can be configured for either  
dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC  
low, the status bits are defined and used internally by the device, allowing easier  
determinationof the validity and use of the given tag data. SFUNC high releases the  
defined internal status bit usage and control, allowing users to configure the status  
bit information to fit their system needs. A synchronous RESET pin, when held low  
at a rising clock edge, will reset all status bits in the array for easy invalidation of all  
tag addresses.  
The MPC27T416 also provides the option for transfer acknowledge (TA)  
generation within the cache tag itself, based upon MATCH, VALID bit, and other  
external inputs provided by the user. This can significantly simplify cache controller  
logic and minimize cache decision time. Match and read operations are both  
asynchronous in order to provide the fastest access times possible, while write  
operations are synchronous for ease of system timing.  
TheMPC27T416usesa5VpowersupplyonV  
andV , withseparateV  
CC  
SS  
CCQ  
pins provided for the outputs to offer compliance with both 5 V TTL and 3.3 V LVTTL  
logic levels. The PWRDN pin offers a low–power standby mode, which provides  
significant system power savings.  
The MPC27T416 is offered in a space saving 80–pin thin quad flat pack (TQFP)  
package.  
•
16K x 16 Configuration:  
– 14 Tag Bits  
– Two Status Bits (Valid and Dirty)  
•
•
•
•
Valid Bit used to Qualify Match Output  
High–Speed Address–to–Match Comparison Times – 9/10/12 ns  
TA Circuitry Included Inside the Cache–Tag for the Highest Speed Operation  
Asynchronous Read/Match Operation and Synchronous Write and Reset  
Operation  
•
•
•
•
Separate Write Enable Pins for Tag Bits and Status Bits  
Separate Output Enable Pins for Tag Bits, Status Bits, and TA  
Synchronous RESET Pin for Invalidation of all Tag Entries  
Dual Chip Selects for Easy Depth Expansion with No Performance  
Degradation  
•
•
•
•
I/O Pins Both 5 V TTL and 3.3 V LVTTL Compatible with V  
PWRDN Pin to Place Device in Low–Power Mode  
Compatible with PowerPC Platform (CHRP)  
Pins  
CCQ  
Packaged in a 80–Pin Thin Quad Flat Pack (TQFP)  
PowerPC is a trademark of IBM Corp.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
4/26/96  
Motorola, Inc. 1996  
1234567...16

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