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MPC2605ZP83R PDF预览

MPC2605ZP83R

更新时间: 2024-10-29 19:56:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
36页 452K
描述
Cache Tag SRAM, 32KX72, 8ns, BICMOS, PBGA241, PLASTIC, BGA-241

MPC2605ZP83R 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:PLASTIC, BGA-241Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.81最长访问时间:8 ns
其他特性:8K X 18 TAGJESD-30 代码:S-PBGA-B241
JESD-609代码:e0长度:25 mm
内存密度:2359296 bit内存集成电路类型:CACHE TAG SRAM
内存宽度:72功能数量:1
端子数量:241字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX72封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA241,19X19,50
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:SRAMs最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:25 mm
Base Number Matches:1

MPC2605ZP83R 数据手册

 浏览型号MPC2605ZP83R的Datasheet PDF文件第2页浏览型号MPC2605ZP83R的Datasheet PDF文件第3页浏览型号MPC2605ZP83R的Datasheet PDF文件第4页浏览型号MPC2605ZP83R的Datasheet PDF文件第5页浏览型号MPC2605ZP83R的Datasheet PDF文件第6页浏览型号MPC2605ZP83R的Datasheet PDF文件第7页 
MPC2605/D  
Rev. 12, 11/2002  
Integrated Secondary Cache  
for Microprocessors That  
Implement PowerPC  
Architecture  
The MPC2605 is a single chip, 256KB integrated look-aside  
cache with copy-back capability designed for applications  
using a 60x bus. Using 0.38 µm technology along with  
standard cell logic technology, the MPC2605 integrates data,  
tag, host interface, and least recently used (LRU) memory  
with a cache controller to provide a 256KB, 512KB, or 1MB  
Level 2 cache with one, two, or four chips on a 64-bit 60x  
bus.  
E  
ZP PACKAGE  
PBGA  
0  
CASE 1138-01  
• Single Chip L2 Cache  
• 66 or 83 MHz Zero Wait State Performance (2-1-1-1 Burst)  
• Four-Way Set Associative Cache Design  
• 32K x 72 Data Memory Array  
• 8K x 18 Tag Array  
• Address Parity Support  
• LRU Cache Control Logic  
• Copy-Back or Write-Through Modes of Operation  
• Copy-Back Buffer for Improved Performance  
• Single 3.3 V Power Supply  
• 5 V Tolerant I/O  
• One-, Two-, or Four-Chip Cache Solution (256KB, 512KB, or 1MB)  
• Single Clock Operation  
• Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)  
• Supports up to Four Processors in a Shared Cache Configuration  
• High Board Density 25 mm 241 PBGA Package  
 

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